Memory architecture with single-port cell and dual-port (read and write) functionality

In a single port memory structure having local and global data sensing, local and global location selecting, and memory modules having groups of memory cells and a memory location, wherein storage of a second datum at a designated memory location is to follow sensing of a first datum at the designated memory location, and wherein the designated memory location develops a “FAILED” condition, a method for substantially simultaneously retrieving a first datum from the designated memory location in the memory module and storing the second datum in the redundant memory location, the method comprising:

• a. locally selecting the designated memory location from which the first datum is to be retrieved;
• b. locally sensing the first datum in the designated memory location (READ operation);
• c. detecting the “FAILED” condition in the designated memory location;
• d. assigning the redundant memory location to represent the designated memory location;
• e. globally selecting the redundant memory location for storing the second datum;
• f. substantially concurrently with the globally selecting, globally sensing the first datum in the designated memory location;
• g. outputting the first datum subsequent to the globally sensing;
• h. inputting the second datum substantially immediately subsequent to the outputting the first datum;
• i. locally selecting the redundant memory location for storing the second datum;
• and
• j. storing the datum in the redundant memory location (WRITE operation).

A method for substantially simultaneously retrieving a first datum from a first memory and storing a second datum in a second memory location, wherein both locations are disposed within a single-port memory structure having local and global data sensing, and local and global location selecting, the method comprising:

• a. locally selecting the first memory location from which the first datum is to be retrieved;
• b. locally sensing the first datum (READ operation) in the first memory location;
• c. globally selecting the second memory location;
• d. substantially concurrently with the globally selecting, globally sensing the first datum at the first memory location;
• e. outputting the first datum subsequent to the globally sensing;
• f. inputting the second datum substantially immediately subsequent to the outputting the first datum;
• g. locally selecting the second memory location;
• and
• h. storing the second datum (WRITE operation) in the second memory location.

A method for providing sequential storage of a first datum in a first memory structure location and a second datum in a second memory structure location within one access cycle of the memory structure, the structure having local and global location selecting, the method comprising:

• a. globally selecting the first memory structure location to which the first datum is to be stored;
• b. precharging bitlines coupled with the memory cells at the first memory structure location (PRECHARGE1 operation);
• c. locally selecting the first memory structure location;
• d. storing the first datum (WRITEI operation) in the first memory structure location;
• e. globally selecting the second memory structure location to which the second datum is to be stored;
• f. substantially concurrently with the globally selecting the second memory structure location, precharging bitlines coupled with the second memory structure location (PRECHARGE2 operation);
• g. locally selecting the second memory structure location;
• and
• h. storing the second datum (WRITE2 operation) in the second memory structure location.

A single-port memory structure having a predetermined memory access speed and a memory access period, comprising:

• a. memory modules having
• (1) memory cells disposed to store data;
• (2) local and global sense amplifiers, the local sense amplifiers being coupled with the memory cells;
• and
• (3) local and global row decoders, the local row decoders being coupled with the memory cells;
• b. local and global sense amplifiers, selected local sense amplifiers being the global sense amplified of selected ones of the memory modules;
• c. local and global row decoders, selected local row decoders being the global row decoders of selected memory modules;
• and
• d. a predecoding circuit coupled with selected global row decoders, wherein the predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory structure access speed, and allowing access to a selected memory cell at least twice during the memory access period, thereby providing dual-port functionality thereby.

In a memory structure comprising memory cells disposed to store data, the structure having a predetermined memory access speed and a memory access period, a method of obtaining dual port functionality comprising the steps of:

• reading a datum from one of the memory cells;
• writing the read datum into one of the memory cells without a separate precharge cycle interposed between the reading and writing;
• and
• completing the reading step and writing step within memory access period.