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US 6,618,300 B2Granted
Semiconductor memory device and method for replacing redundancy circuit
AssigneesNEC Corporation, NEC Electronics Corporation
InventorHiroyuki Yamakoshi
Life of this patent
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Abstract
In a semiconductor memory device, a plurality of banks is arranged on a semiconductor substrate. A plurality of memory array groups is arranged on the plates. Redundant memory cell array groups replace a memory cell array, including a defective memory cell, and are arranged at every plate. Subword selection circuits switch subword selection lines at every plate. Each of the subword selection circuits has a selection unit which selects a subword selection line on the plate belonging thereto and a redundant subword selection line of the redundant memory cell array arranged on the other adjacent plate.
Claims15
A semiconductor memory device comprising:
- a plurality of banks which are arranged on a semiconductor substrate;
- a plurality of plates;
- a plurality of memory array groups which are arranged on the plates;
- redundant memory cell array groups which replace a memory cell array including a defective memory cell and which are arranged at every plate;
- and
- subword selection circuits which switch subword selection lines at every plate;
- wherein each of the subword selection circuits has a selection unit which selects a subword selection line on the plate belonging thereto and a redundant subword selection line of the redundant memory cell array arranged on an adjacent plate;
- and
- wherein the subword selection line is selected by the use of a subword driver, and predetermined redundant subword lines of the memory cell array and the redundant memory cell array are selected after an arbitrary main word line is selected by a row decoder during selecting a word line.
6 more elements
A semiconductor memory device comprising:
- a plurality of plates which are arranged on a semiconductor substrate at every bank, each of the plates including:
- memory cell array groups,
- subword driver groups which select word lines of the memory cell array groups,
- subword driver selection units which select one among the subword driver groups,
- redundant memory cell array groups which replace a memory cell array group including a defective memory cell, and
- redundant subword driver groups which select word lines of the redundant memory cell array groups;
- and
- a redundant subword selection unit which selects one among the redundant subword driver groups;
- wherein the redundant subword selection unit commonly uses the subword drive selection units between the adjacent plates, and is given a subword selection signal generated by the subword selection unit of one plate as a redundant subword selection signal of an adjacent plate in order to control selection of the word lines.
6 more elements
A semiconductor memory device comprising:
- first and second plates which are arranged on a semiconductor substrate at every bank, each of the plates including:
- memory cell array groups,
- subword driver groups which select word lines of the memory cell array groups,
- subword driver selection units which select one among the subword driver groups,
- redundant memory cell array groups which replace a memory cell array group including a defective memory cell,
- redundant subword driver groups which select word lines of the redundant memory cell array groups, and
- a redundant subword selection unit which selects one among the redundant subword driver groups,
- wherein both the subword driver selection unit and the redundant subword selection unit are commonly used by only the subword selection unit;
- wherein the subword selection unit commonly used between the plates is commonly used between the first and second plates;
- and
- wherein the common use between the first and second plates is carried out by the subword selection unit which commonly uses the redundant subword selection lines of the first and second plates in one of the plates for the other.
8 more elements
A semiconductor memory device comprising:
- a plurality of banks which are arranged on a semiconductor substrate;
- a plurality of plates;
- a plurality of memory array groups which are arranged on the plates;
- redundant memory cell array groups which replace a memory cell array including a defective memory cell and which are arranged at every plate;
- and
- subword selection circuits which switch subword selection lines at every plate;
- wherein each of the subword selection circuits has a selection unit which selects a subword selection line on the plate belonging thereto and a redundant subword selection line of the redundant memory cell array arranged on an adjacent plate;
- and
- wherein the subword selection line is selected by the use of a subword driver, and predetermined redundant subword lines of the memory cell array and the redundant memory cell array are selected after an arbitrary main word line is selected by a row decoder during selecting a word line, wherein:
- the selection unit is provided with a logical add between at least a selection signal of a first plate and a selection signal of a second plate as a selection condition signal, a signal connection is carried out between adjacent plates,
- one plate connects the selection signal of the first plate to a selection signal terminal of the first plate while the other plate connects to the selection signal terminal of the other plate
- the other plate connects the selection signal of the second plate to the selection signal terminal of the second plate while the first plate connects to the selection signal terminal of the first plate.
9 more elements
A semiconductor memory device comprising:
- a first memory cell array group and a first redundant memory cell array group which are divided and arranged into a first plate;
- a second memory cell array group and a second redundant memory cell array group which are divided and arranged to a second plate adjacent to the first plate;
- first subword selection circuit corresponding to the first plate;
- a second subword selection circuit corresponding to the second plate;
- a first subword selection signal line which is connected to the first subword selection circuit;
- and
- a second subword selection signal line which is connected to the second subword selection circuit;
- wherein the first and second subword selection signal lines cross a redundant memory cell array of each plate so as to extend in a parallel direction, and are wired to a subword driver on an adjacent plate.
5 more elements
A method of replacing a redundant circuit of a semiconductor memory device, comprising the steps of:
- dividing a memory cell array into a plurality of memory blocks;
- grouping the memory blocks into a plurality of plates;
- arranging a redundant memory block for each plate;
- arranging a subword driver or a redundant subword driver in accordance with the memory block and the redundant memory block in order to perform word selection;
- selecting the block when the memory block includes a defective memory cell;
- and
- replacing the redundant memory block;
- wherein the redundant subword of the plate including the defective cell is mutually selected by the use of a subword selection signal generated by a subword selection circuit of the adjacent plate, and
- whereby, the subword selection circuit is commonly used between the plates so as to replace the redundant memory block.
6 more elements
Dependencies are inferred from the claim text.