Semiconductor memory device with redundancy

A semiconductor memory device, comprising:

• a default array;
• a row redundant array block comprising row redundant arrays that are independent from the default array, for supplementing a deficiency in a row direction, wherein the row redundant array block is mapped so that the column addresses of the default array become row addresses;
• and
• a column redundant array block comprising column redundant arrays that are independent from the default array, for supplementing a deficiency in a column direction, wherein the column redundant array block is mapped so that a portion of the row addresses of the default array become column addresses.

A method for managing a memory array in a semiconductor memory device, wherein the memory array comprises a default array and a redundant array of memory cells, the method comprising the steps of:

• mapping a row redundant array so that column addresses of the default array become row addresses;
• accessing the row redundant array to compensate for a deficiency in a row direction of the default array;
• mapping a column redundant array so that a portion of row addresses of the default array become column addresses;
• accessing the column redundant array to compensate for a deficiency in a column direction of the default array;
• and
• disabling operation of a sense amplifier of the default array during an access of one of the row redundant array and column redundant array.

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for managing a memory array in a semiconductor memory device, wherein the memory array comprises a default array and a redundant array of memory cells, the method steps comprising:

• mapping a row redundant array so that column addresses of the default array become row addresses;
• accessing the row redundant array to compensate for a deficiency in a row direction of the default array;
• mapping a column redundant array so that a portion of row addresses of the default array become column addresses;
• accessing the column redundant array to compensate for a deficiency in a column direction of the default array;
• and
• disabling operation of a sense amplifier of the default array during an access of one of the row redundant array and column redundant array.