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US 6,618,298 B2Granted
Semiconductor memory device
AssigneesHitachi, Ltd., Akita Electronics Co., Ltd.
InventorsKazuki Honma, Masashi Wada, Shuichi Kuwahara
Life of this patent
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Abstract
The semiconductor memory device of the present invention is provided with a switching element comprised of a single channel MOS transistor at a halfway of a path used to transmit a high voltage supplied to the memory array via the external terminal at the time of a test performance, so that the switching element is turned off when a word line is changed to another, thereby resetting of the supply voltage having been required conventionally for each test performance is omitted.
Claims10
A semiconductor memory device, comprising:
- a memory array comprised of a plurality of memory cells, a plurality of selection lines connected to selection terminals of the plurality of memory cells disposed in a first direction, and a plurality of signal lines connected to data input/output terminals of the plurality of memory cells disposed in a second direction, said semiconductor memory device being formed as a semiconductor integrated circuit on a semiconductor chip,
- wherein said semiconductor chip is provided with an external terminal in addition to a power supply terminal via which a supply voltage is supplied for the operations of all the circuits disposed thereon, said external terminal being enabled to supply a first voltage to said memory array at the time of a test performance, said first voltage being different from said supply voltage, and
- wherein a first switching element is provided at a halfway of a path that transmits said first voltage from said external terminal to said memory array, said first switching element comprised of an N-channel or P-channel MOS transistor.
Dependencies are inferred from the claim text.