Method and apparatus for biasing selected and unselected array lines when writing a memory array

In an integrated circuit including a three-dimensional array having at least two planes of write-once passive element memory cells, each memory cell respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of writing a selected memory cell coupled between a selected X-line and a selected Y-line associated with a selected memory plane, said method comprising the steps of:

• biasing the selected X-line to a first voltage;
• biasing the selected Y-line to a second voltage different than the first voltage;
• biasing at least some unselected X-lines associated with the selected memory plane to a third voltage within a range defined by the first and second voltages;
• and
• biasing at least some unselected Y-lines associated with the selected memory plane to a fourth voltage within the range defined by the first and second voltages and substantially different than the first and second voltages;
• wherein the fourth voltage is closer to the first voltage than the second voltage and is offset by a first amount from the first voltage;
• and
• the third voltage is closer to the second voltage than the first voltage and is offset by a second amount from the second voltage.

In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of writing a selected memory cell coupled between a selected X-line and a selected Y-line, said method comprising the steps of:

• biasing the selected X-line to a first voltage;
• biasing the selected Y-line to a second voltage;
• biasing at least some unselected X-lines to a third voltage;
• and
• biasing at least some unselected Y-lines to a fourth voltage;
• wherein the first, second, third, and fourth voltages are each substantially different.

In an integrated circuit including at least one memory sub-array of passive element memory cells, each memory cell within a given sub-array respectively coupled between a respective one of a plurality of X-lines associated with the given sub-array and a corresponding one of a plurality of Y-lines associated with the given sub-array, a method of programming memory cells comprising the steps of:

• for each sub-array having at least one memory cell to be programmed:
• biasing at least some X-lines within the sub-array to a write mode unselected X-line (UXL) voltage and biasing at least some Y-lines within the sub-array to a write mode unselected Y-line (UYL) voltage, both voltages chosen so that a particular voltage lower in magnitude than a programming voltage is impressed across the memory cells coupled respectively therebetween;
• then
• for each of a group of at least one memory cell within the sub-array to be programmed, pulsing its associated X-line to a write-mode selected X-line (SXL) voltage while pulsing its associated Y-line to a write-mode selected Y-line (SYL) voltage, both voltages chosen so that the programming voltage is impressed across the memory cell, for a time sufficient to program the memory cell.

In an integrated circuit including at least one three-dimensional memory sub-array of passive element memory cells arranged in at least two memory planes, each memory cell of a given memory plane within a given sub-array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given sub-array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given sub-array, a method of programming memory cells comprising the steps of:

• for each memory plane within each sub-array having at least one memory cell to be programmed:
• biasing at least some of the X-lines associated therewith to a write mode unselected X-line (UXL) voltage and biasing at least some of the Y-lines associated therewith to a write mode unselected Y-line (UYL) voltage, both voltages chosen so that a particular voltage lower in magnitude than a programming voltage is impressed across the memory cells coupled respectively therebetween;
• then
• for each of a group of at least one memory cell to be programmed within the memory plane and sub-array, pulsing its associated X-line to a write-mode selected X-line (SXL) voltage while pulsing its associated Y-line to a write-mode selected Y-line (SYL) voltage, both voltages chosen so that the programming voltage is impressed across the memory cell, for a time sufficient to program the memory cell,
• wherein the programming voltage is greater in magnitude than the second voltage, and the second voltage is greater in magnitude than both the third and fourth voltages.

An integrated circuit comprising:

• an array of passive element memory cells, each respectively having a first terminal coupled to a respective one of a plurality of X-lines and having a second terminal coupled to a respective one of a plurality of Y-lines;
• a first array support circuit for biasing each X line, when selected during a write mode of operation, to a first voltage and when unselected during a write mode of operation, to a third voltage;
• a second array support circuit for biasing each Y line, when selected during a write mode of operation, to a second voltage and when unselected during a write mode of operation, to a fourth voltage;
• wherein the first voltage is different than the second voltage;
• wherein the third voltage falls within a range defined by the first and second voltages;
• and
• wherein the fourth voltage falls within the range defined by the first and second voltages and is substantially different than the first and second voltages.

An integrated circuit comprising:

• at least one memory sub-array of passive element memory cells arranged in at least one memory plane, each memory cell of a given memory plane within a given sub-array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given sub-array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given sub-array, each of the memory cells having a directionality from a respective first terminal to a respective second terminal thereof;
• array circuitry configured, during a write mode of operation, for biasing the respective first terminal of each selected memory cell within a selected memory plane of a selected sub-array to a first voltage, for biasing the respective second terminal of each selected memory cell within a selected memory plane of a selected sub-array to a second voltage different than the first voltage, for biasing the respective first terminal of at least a group of unselected memory cells within a selected memory plane of a selected sub-array to a third voltage having a value within a range defined by the first and second voltages, and for biasing the respective second terminal of at least a group of unselected memory cells within a selected memory plane of a selected sub-array to a fourth voltage having a value within the range defined by the first and second voltages and substantially different than the first and second voltages.

An integrated circuit comprising:

• at least one memory sub-array of passive element memory cells arranged in at least one memory plane, each memory cell of a given memory plane within a given sub-array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given sub-array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given sub-array, each of the memory cells having a directionality from a respective first terminal to a respective second terminal thereof;
• and
• array circuitry configured, during a write mode of operation for a selected memory plane of a selected sub-array, for impressing a programming voltage in a forward-biased direction across a selected memory cell therewithin, for impressing a second voltage in a reverse-biased direction across unselected memory cells therewithin, for impressing a third voltage in a forward-biased direction across half-selected memory cells coupled to a selected X-line therewithin, and for impressing a fourth voltage in a forward-biased direction across half-selected memory cells coupled to a selected Y-line therewithin;
• wherein the programming voltage is greater in magnitude than the second voltage, and the second voltage is greater in magnitude than both the third and fourth voltages.