Non-volatile memory with block erase
AssigneeMicron Technology, Inc.
InventorBrady L. Keays
Life of this patent
Estimating the term…
Abstract
A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.
Claims9
A method of performing an erase operation on a flash memory block comprising:
- pre-charging flash memory cells arranged in rows in the block to a predetermined level;
- applying at least one first stage erase pulse to the block;
- verifying if each memory cell is erased by row after each first stage erase pulse is applied to the block;
- counting a first number of pulses applied to the block, wherein the first number of pulses applied to the block is the number of pulses used to verify a majority of rows in the block have been erased;
- calculating a second number based on a fraction of the first number, wherein the second number is a maximum number of additional second stage erase pulses that may be applied to the block to try and erase the memory cells in the rows not yet verified as being erased;
- applying at least one second stage erase pulse to the block;
- verifying if each memory cell is erased by row after each second stage erase pulse is applied to the block;
- and
- completing erase of the block when either the second number of second stage erase pulses have been applied to the block or all the rows have been verified as being erased.
A non-volatile memory device comprising:
- a memory block comprised of flash memory cells that are arranged in rows;
- and
- a controller coupled to the flash memory block such that the controller is capable of precharging the flash memory cells, applying a first stage erase pulse to the memory block, verifying erasure of each flash memory cell after application of the first stage erase pulse, counting a first quantity of erase pulses to the memory block, calculating a maximum quantity of second stage erase pulses based on a fraction of the first quantity, applying at least one second stage erase pulse to the memory block, verifying if each memory cell is erased after each second stage erase pulse, and completing erasure of the memory block when either the maximum quantity of second stage erase pulses have been applied to the memory block or all flash memory cells have been verified as being erased.
A flash memory system comprising:
- a processor that generates an erase signal;
- and
- a non-volatile memory device coupled to the processor, the non-volatile memory device comprising:
- a memory block comprised of flash memory cells that are arranged in rows;
- and
- a controller coupled to the flash memory block such that the controller, in response to the erase signal, is capable of precharging the flash memory cells, applying a first stage erase pulse to the memory block, verifying erasure of each flash memory cell after application of the first stage erase pulse, counting a first quantity of erase pulses to the memory block, calculating a maximum quantity of second stage erase pulses based on a fraction of the first quantity, applying at least one second stage erase pulse to the memory block, verifying if each memory cell is erased after each second stage erase pulse, and completing erasure of the memory block when either the maximum quantity of second stage erase pulses have been applied to the memory block or all flash memory cells have been verified as being erased.
Dependencies are inferred from the claim text.