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US 6,618,292 B2Granted
Semiconductor memory device and method of operating the same
AssigneeKabushiki Kaisha Toshiba
InventorKoji Sakui
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device the potential of a semiconductor substrate and that of all of a plurality of word lines are increased to an erase voltage by means of a boosting circuit, and subsequently the potential of the word line selected by a word line selection circuit is decreased, when data of a memory cell is erased.
Claims27
A semiconductor memory device comprising:
- a memory cell array arranged on a semiconductor substrate,
- said memory cell array being formed by arranging a plurality of memory cell units in array,
- each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines;
- a word line selection circuit which selects one of said plurality of word lines;
- a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines;
- and
- a control circuit which controls said boosting circuit, said control circuit increasing the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit and subsequently decreasing the potential of the word line selected by said word line selection circuit.
4 more elements
A semiconductor memory device comprising:
- a memory cell array arranged on a semiconductor substrate,
- said memory cell array being formed by arranging a plurality of NAND type memory cell units in array,
- each of said plurality of NAND type memory cell units being formed by connecting a plurality of rewritable nonvolatile memory cells in series, said plurality of rewritable nonvolatile memory cells being connected respectively to a plurality of word lines,
- each of said plurality of NAND type memory cell units being connected at an end thereof to a plurality of bit lines and at the other end thereof to a common source line;
- a word line selection circuit which selects one of said plurality of word lines;
- a bit line selection circuit which selects one of said plurality of bit lines;
- a sense amplifier circuit connected to said plurality of bit lines;
- said sense amplifier circuit having a latch function;
- a transfer gate being arranged between said sense amplifier circuit and said plurality of bit lines;
- a boosting circuit which boosts the potentials of said semiconductor substrate and said plurality of word lines;
- and
- a control circuit which controls said boosting circuit,
- said control circuit increasing the potentials of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit and subsequently decreasing the potential of the word line selected by said word line selection circuit.
10 more elements
A method of operating a semiconductor memory device,
- said semiconductor memory device including
- a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of memory cell units in array, each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines,
- a word line selection circuit which selects one of said plurality of word lines, a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines, and
- a control circuit which controls said boosting circuit;
- said method comprising
- increasing the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and subsequently decreasing the potential of the word line selected by said word line selection circuit under the control of said control circuit.
3 more elements
A method of operating a semiconductor memory device,
- said semiconductor memory device including
- a memory cell array arranged on a semiconductor substrate, said memory cell array being formed by arranging a plurality of NAND type memory cell units in array, each of said plurality of NAND type memory cell units being formed by connecting a plurality of rewritable nonvolatile memory cells in series, said plurality of rewritable nonvolatile memory cells being connected respectively to a plurality of word lines, each of said plurality of NAND type memory cell units being connected at an end thereof to a plurality of bit lines and at the other end thereof to a common source line,
- a word line selection circuit which selects one of said plurality of word lines,
- a bit line selection circuit which selects one of said plurality of bit lines,
- a sense amplifier circuit connected to said plurality of bit lines, said sense amplifier circuit having a latch function, a transfer gate being arranged between said sense amplifier circuit and said plurality of bit lines,
- a boosting circuit which boosts the potentials of said semiconductor substrate and said plurality of word lines, and
- a control circuit which controls said boosting circuit;
- said method comprising
- increasing the potentials of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and subsequently decreasing the potential of the word line selected by said word line selection circuit.
6 more elements
A semiconductor memory device comprising:
- a memory cell array arranged on a semiconductor substrate,
- said memory cell array being formed by arranging a plurality of memory cell units in array,
- each of said plurality of memory cell units being formed by connecting a plurality of rewritable memory cells to each of a plurality of word lines;
- a word line selection circuit which selects one of said plurality of word lines;
- a boosting circuit which boosts the potential of said semiconductor substrate and that of said plurality of word lines;
- and
- a control circuit which controls said boosting circuit, said control circuit being configured to increase the potential of said semiconductor substrate and that of all of said plurality of word lines to an erase voltage by said boosting circuit, and to subsequently decrease the potential of the word line selected by said word line selection circuit while maintaining the potential of the word lines other than the selected word line.
4 more elements
Dependencies are inferred from the claim text.