Global/local memory decode with independent program and read paths and shared local decode
AssigneeIntel Corporation
InventorDaniel R. Elmhurst
Life of this patent
Estimating the term…
Abstract
A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.
Claims6
An apparatus, comprising:
- a memory circuit including a global read selection line to provide a read voltage, a global program selection line to provide a program voltage, and a plurality of memory blocks, each block being coupled to the global read selection line and to the global program selection line, each block including
- a first regional selection line coupled to a plurality of first local selection lines and a second regional selection line coupled to a plurality of second local selection lines;
- a first read transistor coupling the global read selection line to the first regional selection line to switchably apply the read voltage to the first regional selection line and a second read transistor coupling the global read selection line to the second regional selection line to switchably apply the read voltage to the second regional selection line;
- a first program transistor coupling the global program selection line to the first regional selection line to switchably apply the program voltage to the first regional selection line and a second program transistor coupling the global program selection line to the second regional selection line to switchably apply the program voltage to the second regional selection line;
- a first plurality of local selection transistors, each coupling the first regional selection line to one of the plurality of first local selection lines;
- and
- a second plurality of local selection transistors, each coupling the second regional selection line to one of the plurality of second local selection lines.
Dependencies are inferred from the claim text.