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US 6,618,286 B2Granted
Non-volatile semiconductor memory device with a memory array preventing generation of a through current path
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiroshi Kato, Tsukasa Ooishi
Life of this patent
Estimating the term…
Abstract
A NROM(R) memory array is divided into memory blocks. An isolating portion for electrically isolating corresponding memory blocks from each other is formed in the boundary region between adjacent memory blocks. When read or write operation is performed one bit per memory block, a through current path can be prevented from being generated in the read or write operation.
Claims18
A non-volatile semiconductor memory device, comprising:
- a memory array including a plurality of non-volatile memory transistor cells arranged in a matrix, said plurality of non-volatile memory transistor cells each having a threshold voltage according to a storage data level, wherein
- said memory array is divided into a plurality of memory blocks, each of said plurality of memory blocks including
- a plurality of memory cell columns, and
- a plurality of bit lines arranged along column direction on both sides of each of said plurality of corresponding memory cell column respectively, each of the bit lines arranged between adjacent two memory cell columns being shared by said adjacent two memory cell columns, and
- said memory array includes a plurality of isolating portions each provided between adjacent two memory blocks, for electrically isolating said two memory blocks from each other.
2 more elements
Dependencies are inferred from the claim text.