High density ROM architecture with inversion of programming

A ROM for storing information including:

• a substrate with bit cell regions disposed therein;
• a plurality of word lines;
• a plurality of bit lines wherein the plurality of word lines and the plurality of bit lines form intersection areas between the bit lines and the word lines, wherein the intersection areas form a plurality of nodes which correspond to the bit cell regions disposed in the substrate;
• a sensing circuit coupled to the plurality of bit lines;
• a first bit cell region corresponding to a first node at an intersection area between a first bit line and a first word line, wherein a first transistor having a drain, a channel, and a source is disposed in the first bit cell region, and wherein a first contact couples the first bit line to the drain of the first transistor;
• a second bit cell region corresponding to a second node at an intersection area between the first bit line and a second word line, wherein an insulating layer is disposed between the second bit cell region and the first bit line;
• a third bit cell region corresponding to a third node at an intersection area between a second bit line and a third word line, wherein a second transistor having a drain, a channel, and a source is disposed in the third bit cell region, and wherein a second contact couples the second bit line to drain of the second transistor;
• a fourth bit cell region corresponding to a fourth node at an intersection area between the second bit line and a fourth word line, wherein an insulating layer is disposed between the fourth bit cell region and the second bit line;
• and
• wherein in response to a first voltage applied to the first word line the sensing circuit detects a first current flow through the first transistor and outputs a first signal, and in response to a second voltage applied to the second word line the sensing circuit detects an absence of current in the second bit cell region and outputs a second signal, and in response to a third voltage applied to the third word line the sensing circuit detects a second current flow through the second transistor and outputs the second signal, and in response to a fourth voltage applied to the fourth word line the sensing circuit detects an absence of current in the fourth bit cell region and outputs the first signal.

A ROM system for storing information in bit cells, the system including:

• a substrate having a plurality of bit cell regions;
• a plurality of sectors, wherein each sector includes a plurality of columns of bit cells;
• wherein the plurality of sectors includes a first sector which includes a first column of bit cells, wherein a first bit cell in the first column of bit cells includes a first bit cell region disposed in the substrate, wherein a first transistor is disposed in the first bit cell region, wherein a second bit cell in the first column of bit cells includes a second bit cell region disposed in the substrate, wherein the second bit cell region consists of an isolating dielectric region;
• wherein the plurality of sectors includes a second sector which includes a second column of bit cells, wherein a third bit cell of the second column of bit cells includes a third bit cell region disposed in the substrate, wherein the third bit cell region consists of an isolating dielectric region, wherein a fourth bit cell of the second column of bit cells includes a fourth bit cell region disposed in the substrate, wherein a second transistor is formed in the fourth bit cell region;
• a first sensing circuit wherein the first sensing circuit is coupled to the first column of bit cells, wherein in response to a voltage applied to the first bit cell the sensing circuit detects a current flow through the first transistor and outputs a first signal, wherein in response to a voltage applied to the second bit cell the sensing circuit detects an absence of current in the second bit cell, and outputs a second signal;
• a second sensing circuit wherein the second sensing circuit is coupled to the second column of bit cells, wherein in response to a voltage applied to the third bit cell, the second sensing circuit detects an absence of current flow in the third bit cell and outputs the first signal, wherein when a voltage is applied to the fourth bit cell the second sensing circuit detects current flow through the second transistor and outputs the second signal.