Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)

A method for determining a desired operating impedance for a content addressable memory (CAM) having a match line circuit coupled thereto, the CAM further having a plurality of discrete selectively adjustable impedance values associated with a pull-up device within the match line circuit, the method comprising:

• applying to a reference circuit, a test impedance value, said test impedance value controlled by a binary count;
• determining based upon said applied test impedance value, whether said reference circuit is in either a first state or a second state;
• incrementing said binary count if said reference circuit is in said first state and decrementing said binary count if said reference circuit is in said second state, thereby increase said applied test impedance value if said binary count is incremented and decreasing said applied test impedance value if said binary count if decremented;
• determining a condition in which said reference circuit oscillates between said first state and said second state;
• and
• storing a pair of binary count values, one of said pair of binary count values representing a first impedance value which causes said reference circuit to change from said first state to maid second state, the other of said air of binary count values representing a second impedance value which causes said reference circuit to change from said first stale to said second state;
• adjusting said lower of said stored pair of binary count values so as to create a buffered count, said buffered count used in applying the desired operating impedance to said match line circuit;
• wherein the desired operating impedance for the computer memory circuit corresponds to the lower of said stored pair of binary count values.

An apparatus for automatically adjusting the margin of an operating impedance for an operating circuit, the operating circuit having a plurality of discrete, selectively adjustable impedance values associated therewith, the apparatus comprising:

• a reference circuit, said reference circuit having a test impedance value applied thereto, said test impedance value being controlled by a binary count;
• a counter for incrementing and decrementing said binary count;
• a first storage device, coupled to an output of said reference circuit, said storage device storing a signal which controls the direction of said binary count;
• incrementing said binary count if said reference circuit is in said first state and decrementing said binary count if said reference circuit is in said second state, thereby increasing said applied test impedance value if said binary count is incremented and decreasing said applied test impedance value if said binary count is decremented;
• determining a condition in which said reference circuit oscillates between said first state and said second state;
• a second storage device, said second storage device storing a pair of binary count values, one of said pair of binary count values representing a first impedance value which causes said reference circuit to change from said first state to said second state, the other of said pair of binary count values representing a second impedance value which causes said reference circuit to change from said first state to said second state;
• and
• an adder for adjusting the lower of said stored pair of binary count values so as to create a buffered count;
• wherein the desired operating impedance for the operating circuit corresponds to said buffered count.

An apparatus for automatically adjusting the pull-up margin of a match line circuit in a circuit in a content addressable memory (CAM), the apparatus comprising:

• a reference circuit said reference circuit having a test impedance value applied thereto, said test impedance value home controlled by a binary count;
• a counter fir incrementing and decrementing said binary count;
• a first storage device, coupled to an output of maid reference circuit said storage device storing signal which controls the, direction of said binary count;
• said counter incrementing said binary count if said reference circuit is in said first state and decrementing said binary count if said reference circuit is in said second state, thereby increasing said applied test impedance value if said binary count is incremented and decreasing said applied test impedance value if said binary count is decremented;
• a comparator for determining condition in which said reference circuit oscillates between said first state and said second state;
• and
• A second storage device, said second storage device storing a pair of binary count values, one of said pair of binary count values representing a first impedance value which causes aid reference circuit to change from said first state to said second state, the other of said pair of binary count values representing a second impedance value which causes said reference circuit to change from said first state to said second state;
• adjusting said lower of said stored pair of binary count values so as to crests a buffered count, said buffered count used in applying the desired operating impedance to the match line circuit;
• wherein the desired operating impedance for the operating circuit corresponds to the lower of said stored pair of binary count values.