Method for high-density, low-via-count, decoupling capacitor placement
AssigneeHewlett-Packard Development Company, L.P.
InventorsRobert J. Blakely, John S. Atkinson
Life of this patent
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Abstract
A capacitor mounting method and resulting printed circuit board that increases the mounting density of both vias and decoupling capacitors is presented. Vias are shared between capacitors mounted on the top and bottom of the printed circuit board. This arrangement allows increased decoupling capacitor density and avoids the current doubling problem when shared vias are connected with capacitors installed on the same side of the board.
Claims8
A printed circuit board, comprising:
- a first metal layer;
- a second metal layer;
- a metal power layer;
- a metal ground layer;
- four decoupling capacitors, C1, C2, C3 and C4, mounted to said printed circuit board, decoupling capacitors C1 and C3 mounted on said first metal layer and decoupling capacitors C2 and C4 mounted on said second metal layer;
- a via 1 electrically connecting said first metal layer to said metal power layer;
- a via 2 electrically connecting said second metal layer to said metal ground layer;
- a plurality of vias 4, 5 and 8 electrically connecting said first metal layer and said second metal layer to said metal power layer;
- a plurality of vias 3, 6, and 7 electrically connecting said first metal layer and said second metal layer to said metal ground layer;
- a via 9 electrically connecting said second metal layer to said metal power layer;
- a via 10 electrically connecting said first metal layer to said metal ground layer;
- decoupling capacitor C1 having a first terminal electrically connected to via 1 and via 4 and a second terminal electrically connected to via 3 and via 6;
- decoupling capacitor C2, having a first terminal electrically connected to via 4 and via 5 and a second terminal electrically connected to via 2 and via 3;
- decoupling capacitor C3 having a first terminal electrically connected to via 5 and via 8 and a second terminal electrically connected to via 7 and via 10;
- and
- decoupling capacitor C4 having a first terminal electrically connected to via 8 and via 9 and a second terminal electrically connected to via 6 and via 7.
A printed circuit board, comprising:
- a first metal layer;
- a second metal layer;
- a metal power layer;
- a metal ground layer;
- a plurality of decoupling capacitors, represented by an integer, n (wherein n>1), wherein each decoupling capacitor is individually numbered by a second integer, i (wherein i=1, 2, 3, . . . , n), mounted to said printed circuit board, odd numbered decoupling capacitors being mounted on said first metal layer and even numbered decoupling capacitors being mounted on said second metal layer;
- a plurality (2n+2)/2 of positive vias electrically connecting said first metal layer and said second metal layer to said metal power layer;
- a plurality (2n+2)/2 of negative vias electrically connecting said first metal layer and said second metal layer to said metal ground layer;
- odd numbered decoupling capacitors having their first terminals electrically connected to positive vias 2i−1 and 2i+2 and their second terminals electrically connected to negative vias 2i+1 and 2i+4;
- even numbered decoupling capacitors having their first terminals electrically connected to positive vias 2i and 2i+1 and their second terminals electrically connected to negative vias 2i−2 and 2i−1.
A method for placing decoupling capacitors on a printed circuit board, said printed circuit board comprising a first metal layer, a second metal layer, a metal power layer, and a metal ground layer, said method comprising the steps of:
- providing a plurality of positive vias for electrically connecting said first metal layer and said second metal layer to said metal power layer;
- providing a plurality of negative vias for electrically connecting said first metal layer and said second metal layer to said metal ground layer;
- placing a plurality of capacitors represented by an integer, n (wherein n>1),on said printed circuit board such that at least (2n−2)/2 positive vias and (2n−2)/2 negative vias are shared among said n capacitors.
A method for placing a plurality of decoupling capacitors, represented by an integer, n (wherein n>1), wherein each decoupling capacitor is individually numbered by a second integer, (wherein i=1, 2, 3, . . . , n),on a printed circuit board, said printed circuit board comprising a first metal layer, a second metal layer, a metal power layer and a metal ground layer, said method comprising the steps of:
- providing a plurality of vias for electrically connecting said first metal layer and said second metal layer to said power layer;
- providing a plurality of vias for electrically connecting said first metal layer and said second metal layer to said ground layer;
- placing said n decoupling capacitors on said printed circuit board to share vias, whereby:
- the first terminals of decoupling capacitors, i, having odd numbers (i=1, 3, 5, . . . , n−1) are electrically connected to vias numbered 2i−1 and 2i+2, the second terminals thereof are electrically connected to vias numbered 2i+1 and 2i+4, the first terminals of decoupling capacitors, i, having even numbers (i=2, 4, 6, . . . , n) are electrically connected to vias numbered 2i and 2i+1, and the second terminals thereof are electrically connected to vias numbered 2i−2 and 2i−1.
Dependencies are inferred from the claim text.