Double triggering mechanism for achieving faster turn-on

Abstract

An ESD protection circuit includes a SCR and a switching means, such as a MOS transistor connected to the SCR so that the SCR is turned on by the switching means to allow an ESD pulse to pass from a Pad line to a grounded VSS line and thereby dissipate the ESD pulse. The SCR is connected between the Pad line and the VSS line. One MOS switching means is connected between the Pad line and the SCR and has a gate which is connected to a VDD line which maintains the switch in open condition during normal VDD bias conditions. An ESD pulse applied to the Pad line, the switch is preconditioned in ON mode allowing the SCR to be predisposed to conduction to allow the ESD pulse to flow to the VSS line.

Dependencies are inferred from the claim text.