Image display device and image display method

An image display device having a plurality of pixels in matrix that are defined by a plurality of data signal lines and a plurality of scanning signal lines intersecting with said plurality of data singal lines, a data signal line driving circuit for feeding image signals to the data signal lines, and a scanning signal line driving circuit for feeding a scanning signal to the scanning signal lines, said image display device comprising a precharge circuit,

• wherein said precharge circuit includes:
• a reference signal input section, to which at least one precharge reference potential is inputted;
• a control signal input section, to which at least one control signal is inputted;
• a plurality of signal delay sections for sequentially delaying an output of said control signal input section;
• and
• a reference signal switching section for switching, in accordance with outputs of said signal delay sections, between a state of outputting the precharge reference potential of said reference signal input section to each of said data signal lines and a state of non-outputting the same thereto,
• wherein timings of signal input to said reference signal switching section are delayed by said signal delay sections so that timings at which the precharge reference potential is inputted to said data signal lines are sequentially delayed from center of a display screen to ends on both sides thereof.

An image display method, for displaying an image on an image display device with a plurality of pixels in matrix that are defined by a plurality of data signal lines, to which image signals are fed, and by a plurality of scanning signal lines intersecting with said plurality of data singal lines, to which a scanning signal is fed, said image display method having the step of writing the image signals to the data signal lines after writing a precharge reference potential from a precharge circuit into each of the data signal lines,

• wherein:
• timings of write of the percharge reference potential fed from the precharge circuit into the data signal lines are varied so that at least two timings are available;
• and
• outputting of the precharge reference potential to each data signal line is simultaneously stopped.