Capacitor mismatch independent gain stage for differential pipeline analog to digital converters

An apparatus for producing digital output signals from a differential analog input signal in a pipelined converter that includes a sample mode and a hold mode, the differential analog input signal including a positive input signal and a negative input signal, the apparatus comprising:

• a first capacitor circuit that is coupled to the differential analog input signal during the sample mode such that the first capacitor circuit is charged by the positive input signal;
• a second capacitor circuit that is coupled to the differential analog input signal during the sample mode such that the second capacitor circuit is charged by the positive input signal;
• a third capacitor circuit that is coupled to a differential common signal during the sample mode such that the third capacitor is substantially discharged;
• a fourth capacitor circuit that is coupled to the differential analog input signal during the sample mode such that the fourth capacitor circuit is charged by the negative input signal;
• a fifth capacitor circuit that is coupled to the differential analog input signal during the sample mode such that the fifth capacitor circuit is charged by the negative input signal;
• a sixth capacitor circuit that is coupled to the differential common signal during the sample mode such that the sixth capacitor is substantially discharged with respect to the third capacitor circuit;
• a comparator circuit that is coupled to the differential analog input signal, and first and second sampling reference signals that are pre-selected to minimize transition height errors, the comparator circuit providing an output code in response to the differential analog input signal and the first and second sampling reference signals, wherein the output code corresponds to one of at least three operating regions for the differential analog input signals during the sample mode;
• a differential amplifier circuit that includes a first input, a second input, and first and second outputs that are arranged to provide a positive residue signal and a negative residue signal, respectively, during the hold mode, wherein the positive and negative residue signal comprise a differential residue signal in the pipelined converter;
• a first selection circuit that is arranged to couple a selected one of the first, second, and third capacitance circuits between the first input and the first output of the differential amplifier circuit in response to the output code during the hold mode;
• a second selection circuit that is arranged to couple the other of the first, second, and third capacitor circuits between a respective hold reference signal and the first input of the differential amplifier circuit, wherein the hold reference signals and the selected capacitor are determined by the output code;
• a third selection circuit that is arranged to couple a selected one of the fourth, fifth, and sixth capacitance circuits between the second input and the second output of the differential amplifier circuit in response to the output code during the hold mode;
• and
• a fourth selection circuit that is arranged to couple the other of the fourth, fifth, and sixth capacitor circuits between a respective hold reference signal and the second input of the differential amplifier circuit, wherein the hold reference signals and the selected capacitor are determined by the output code.