Return to zero and sampling pulse generating circuits and method for direct digital up conversion
OwnerJames J. Komiakinventor
Life of this patent
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Abstract
Direct up-conversion of a signal is accomplished using a sampling pulse generator circuit and a gated differential amplifier, enabled by the sampling signal. When not enabled, the output of the differential amplifier is pulled to zero. The sampling pulse is generated from a base frequency sine wave which is squared with a limiting amplifier, and further passed through one or more frequency doublers producing a times two signal, a times four signal and so on. The squared base frequency and frequency doubled signals are logically ORed to produce a short duration pulse which repeats at the frequency of the base signal. The resulting output is an amplitude modulated pulse doublet time domain waveform.
Claims27
A method comprising:
- in an electronic circuit, applying at least a first FDLA to a first pulse stream to derive a second pulse stream;
- deriving a sampling pulse stream from a logical NOR of at least the first and second pulse streams;
- using the sampling pulse stream to enable an output of a gated differential amplifier.
A circuit comprising:
- at least a first pulse stream;
- at least a first FDLA receiving as an input the at least first pulse stream and an output providing a second pulse stream;
- a logical NOR circuit receiving as input the at least the first and second pulse streams and providing a sampling pulse stream as an output;
- a gated differential amplifier having the sampling pulse stream as a control input.
A system comprising:
- an electrical circuit comprising at least a first FDLA having an input and an output, further comprising a logical NOR circuit and a gated differential amplifier;
- wherein a first pulse train applied to the input of the at least first FDLA produces a second pulse train at the output of the at least first FDLA;
- and wherein at least the first and second pulse trains comprise inputs to the logical NOR circuit and wherein the output of the logical NOR circuit comprises a control signal;
- a return-to-zero circuit comprising a gated differential amplifier having an input and an output and a control input connected to the control signal, wherein the output of the gated differential amplifier follows the input of the gated differential amplifier when the control signal is in a first logical state, and wherein the output of the gated differential amplifier is pulled toward zero when the control signal is in a second logical state.
Dependencies are inferred from the claim text.