Phase locked loop circuits, systems, and methods

Abstract

A phase locked loop in an imaging system is used to generate signals on one of eight equal phase steps within a clock period. The phase locked loop outputs eight clock phases, or four clock phases and their complements, each running at the pixel rate, eliminating the need for higher speed circuitry. According to one embodiment, the phase locked loop employs an oscillator with three inverting stages and one non-inverting stage. The output of each stage is shifted in phase 45 degrees from the previous one, in terms of pixel clock rate. Differential stages are employed so that the delay of the inverting and non-inverting stage are the same. According to the present invention, the output of the last stage is swapped onto the input of the first stage, making it non-inverting without path delay, permitting oscillation with each stage's output remaining at 45 degrees of the previous stage's phase.

Dependencies are inferred from the claim text.