System and method for wide dynamic range clock recovery

A phaselocked loop for locking an output signal to an input signal comprising:

• a primary phase detector for receiving an input signal, and for combining the input signal with a feedback signal to generate a phase difference signal;
• a gain equalizer for normalizing the phase difference signal by a signal strength indicator generated as a function of the amplitude of the input signal;
• and
• an oscillator for providing the output signal bused on the normalized phase difference signal, and for providing the output signal as the feedback signal.

A method for recovering a clock signal from an input data signal comprising:

• receiving an input data signal at a primary phase detector, and combining the input data signal with a feedback signal to generate a phase difference signal;
• receiving the input data signal at an auxiliary phase detector, and combining the input data signal with the feedback signal to generate a signal strength indicator that is a function of the amplitude of the input data signal;
• normalizing the phase difference signal by the signal strength indicator at a gain equalizer;
• and
• providing the clock signal at an oscillator based on the normalized phase difference signal, and providing the clock signal as the feedback signal.

A method for locking an output signal to an input signal in a phaselocked loop comprising:

• receiving an input signal at a primary phase detector, and combining the input signal with a feedback signal to generate a phase difference signal;
• normalizing the phase difference signal by a signal strength indicator generated as a function of the amplitude of the input signal;
• and
• providing the output signal at an oscillator based on the normalized phase difference signal, and providing the output signal as the feedback signal.

A clock recovery system for recovering a clock signal from an input data signal comprising:

• a primary phase detector for receiving an input data signal, and for combining the input data signal transmitted at a carrier band rate with a feedback signal to generate a phase difference signal;
• an auxiliary phase detector for receiving the input data signal, and for combining the input data signal with the feedback signal to generate a signal strength indicator that is a function of the amplitude of the input data signal;
• a gain equalizer for normalizing the phase difference signal by the signal strength indicator, wherein the normalizing is conducted at a baseband rate of the carrier band rate;
• and
• an oscillator for providing the clock signal based on the normalized phase difference signal, and for providing the clock signal as the feedback signal.

A method for recovering a clock signal from an input data signal comprising:

• receiving, at a carrier band rate, an input data signal at a primary phase detector, and combining the input data signal with a feedback signal to generate a phase difference signal;
• receiving the input data signal at an auxiliary phase detector, and combining the input data signal with the feedback signal to generate a signal strength indicator that is a function of the amplitude of the input data signal;
• normalizing, at a baseband rate of the carrier band rate, the phase difference signal by the signal strength indicator at a gain equalizer;
• and
• providing the clock signal at an oscillator based on the normalized phase difference signal, and providing the clack signal as the feedback signal.