Low power wide swing current mirror
AssigneeZarlink Semiconductor (U.S.) Inc.
InventorReghu Rajan
Life of this patent
Estimating the term…
Abstract
A low power wide swing current mirror circuit wherein the signal current is separated from the bias current, and a bias current sink is connected in parallel with a current mirror so as to shunt the bias current to the circuit common.
Claims15
A current mirror circuit, comprising:
- a bias current input port;
- a signal current input port;
- an output current port;
- a mirroring circuit, receiving said bias current and said signal, wherein said bias current biases at least one mirrored transistor in said mirroring circuit;
- and
- a bias current sink, connected to said mirroring circuit so as to shunt at least some of said bias current to circuit common such that essentially no bias current is mirrored to said output current port.
A wide swing current mirror circuit, having an input stage and an output stage, wherein a bias current that biases at least one transistor in said input stage is separated from a signal current at said input stage, and wherein a bias current sink is connected in parallel with at least a portion of said input stage, such that essentially no bias current is mirrored to said output stage.
A method of reducing power consumption in a current mirror, comprising combining both a bias current and a signal current in a mirroring circuit, and routing said bias current and said signal current to circuit common via different paths, such that essentially no bias current is mirrored to an output of said current mirror.
A circuit for mirroring an electrical current, comprising:
- a bias current input terminal;
- a signal current input terminal;
- a first transistor having a biased gate terminal, a drain terminal, and a source terminal, wherein said drain terminal receives said bias current;
- a second transistor having a gate terminal connected to said gate terminal of said first transistor, a drain terminal, and a source terminal;
- a third transistor, having a gate terminal, a drain terminal, and a source terminal, wherein said drain terminal is connected to said source terminal of said first transistor, said gate terminal is connected to said drain terminal of said first transistor, and said source terminal is connected to ground;
- a fourth transistor, having a drain terminal connected to said source terminal of said second transistor, a gate terminal connected to said gate terminal of said third transistor, and a source terminal connected to ground;
- and
- a fifth transistor, having a drain terminal connected to said drain terminal of said third transistor, a source terminal connected to said source terminal of said third transistor, and a gate terminal receiving a bias voltage input, wherein said drain terminal of said third transistor and said drain terminal of said fifth transistor receive said signal current.
A current mirror circuit, comprising:
- a transistor pair forming a current mirror and configured to receive a bias current and an input current, wherein said bias current biases at least one transistor in said current mirror;
- and
- means for sinking at least some of said bias current to circuit common around said transistor pair.
A current mirror circuit comprising:
- a first mirrored input transistor receiving both a signal current and a bias current;
- a first mirroring output transistor;
- and
- a bias current sink transistor connected in parallel with said first mirrored input transistor so as to shunt at least a portion of said bias current from said first mirrored input transistor.
A current mirror circuit, comprising:
- a bias current input port;
- a signal current input port;
- an output current port;
- at least one mirrored transistor, receiving said bias current and said signal current;
- and
- a bias current sink, connected to said signal current input port and said mirroring circuit such that essentially no bias current is mirrored to said output current port.
Dependencies are inferred from the claim text.