Pass gate multiplexer circuit with reduced susceptibility to single event upsets
AssigneeXilinx, Inc.
InventorTrevor J. Bauer
Life of this patent
Estimating the term…
Abstract
A multiplexer circuits for programmable logic devices (PLDs) reduced susceptibility to single event upsets. The pass gate multiplexer circuit has N input circuits having pass gate and N memory cells controlling the pass gates. Each path between an input terminal and the output node includes two pass gates controlled by different memory cells. Therefore, a single event upset that inadvertently enables a pass gate can only short two input terminals when the other,pass gate in the affected input path is also enabled by its associated memory cell. Therefore, the multiplexer circuit with two pass gates in each input path reduces the susceptibility to single event upsets by a factor of (N−4)/N.
Claims17
A multiplexer circuit having reduced susceptibility to single event upsets, comprising:
- N input circuits, where N is an integer greater than four, each input circuit comprising:
- an input terminal,
- a first pass gate coupled to the first input terminal and having a gate terminal,
- a second pass gate coupled to the first pass gate and having a gate terminal, and
- an output terminal coupled to the second pass gate;
- N memory cells susceptible to the single event upsets, each memory cell being coupled to the gate terminal of a respective one of the pass gates of two respective different input circuits within the N input circuits;
- and
- an output node coupled to the output terminals of each of the N input circuits.
A multiplexer circuit having reduced susceptibility to single event upsets, comprising:
- N input terminals, where N is an integer greater than four;
- an output node;
- N first pass gates coupled between the N input terminals and the output node, each of the N first pass gates having a different associated input terminal and further having a gate terminal;
- N second pass gates each coupled in series with an associated one of the N first pass gates and forming therewith a pass gate pair coupled between the associated input terminal and the output node, each of the N second pass gates having a gate terminal;
- and
- N memory cells susceptible to the single event upsets, each memory cell having an output terminal coupled to the gate terminals of an associated one of the N first pass gates and an associated one of the N second pass gates,
- wherein each of the pass gate pairs includes their associated first and second pass gates having gate terminals coupled to different ones of the N memory cells, respectively.
A system controlled by configuration memory cells susceptible to single event upsets, the system comprising:
- a plurality of programmable logic blocks;
- a plurality of interconnect lines;
- and
- a plurality of multiplexer circuits programrably coupling the interconnect lines to each other and to the logic blocks, each of the multiplexer circuits comprising:
- N input terminals, where N is an integer greater than four;
- an output node;
- N first pass gates coupled between the N input terminals and the output node, each of the N first pass gates having a different associated input terminal and further having a gate terminal;
- N second pass gates each coupled in series with associated one of the N first pass gates and forming therewith a pass gate pair coupled between the associated input terminal and the output node, each of the N second pass gates having a gate terminal;
- and
- N configuration memory cells susceptible to the single event upsets, each configuration memory cell having an output terminal coupled to the gate terminals of an associated one of the N first pass gates and an associated one of the N second pass gates,
- wherein each of the pass gate pairs includes their associated first and second pass gates having gate terminals coupled to different ones of the N configuration memory cells, respectively.
Dependencies are inferred from the claim text.