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US 6,617,911 B2Granted
Reducing output capacitance of digital-to-time domain converter for very high frequency digital waveform synthesis
AssigneeIntel Corporation
InventorMel Bazes
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Abstract
In one embodiment, N transmission gates having N outputs transfer one of N pattern inputs to a first output based on an active signal from N select signals. The N outputs are connected together to form the first output and has an output capacitance. An amplifier circuit having a gain is coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain. The amplifier circuit generates an output signal.
Claims33
An apparatus comprising:
- N transmission gates having N outputs to transfer one of N pattern inputs to a first output based on an active signal from N select signals, the N outputs being connected together to form the first output and having an output capacitance;
- and
- an amplifier circuit having a gain and coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain, the amplifier circuit generating an output signal.
A method comprising:
- transferring one of N pattern inputs to a first output based on an active signal from N select signals using N transmission gates having N outputs, the N outputs being connected together to form the first output and having an output capacitance;
- and
- reducing the output capacitance by an amount approximately equal to a gain using an amplifier circuit having the gain, the amplifier circuit generating an output signal.
A circuit comprising:
- a synchronous delay line to generate N tap signals in response to a reference signal;
- a pattern generator to generate N pattern inputs;
- and
- a digital-to-time domain converter (DTC) coupled to the synchronous delay line and the pattern generator to generate an output signal from the N tap signals, the output signal being synchronized by the N pattern inputs, the DTC comprising:
- N transmission gates having N outputs to transfer one of the N pattern inputs to a first output based on an active signal from N select signals, the N outputs being connected together to form the first output and having an output capacitance, and
- an amplifier circuit having a gain and coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain, the amplifier circuit generating an output signal.
3 more elements
Dependencies are inferred from the claim text.