Switched-capacitor circuits with reduced distortion
AssigneeCirrus Logic, Inc.
InventorsAxel Thomsen, Sherry Xiao hong Wu, John Laurence Melanson
Life of this patent
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Abstract
A switched capacitor circuit 300, including a sampling capacitor 303, switches 301, 304 for charging the sampling capacitor 303 during a charging phase, and switches 302, 305 for transferring charge from the sampling capacitor 303 to a load 313 in the feedback loop of an operational amplifier 312 during a dump phase. Circuitry 701 controls the discharge of sampling capacitor 303 during the dump phase to minimize transients at the input of the operational amplifier 312 and thereby minimize input threshold voltage variation.
Claims21
A switched capacitor circuit including a sampling capacitor, switches for charging the sampling capacitor during a charging phase and switches for transferring charge from the sampling capacitor to a load in a feedback loop of an operational amplifier during a dump phase comprising:
- circuitry for slowing discharge of said sampling capacitor during said dump phase by increasing a time constant associated with the sampling capacitor to minimize transients at said input of said operational amplifier.
A switched capacitor integrator, comprising:
- first switches for sampling at least one signal onto at least one sampling capacitor during a first operational phase;
- an operational amplifier including an input summing node;
- an integration capacitor coupling an output of the operational amplifier and the input summing node;
- second switches for transferring charge sampled onto the at least one sampling capacitor to the integration capacitor node during a second operational phase;
- and
- circuitry for reducing a continuous rate of charge transfer between the at least one sampling capacitor and the integration capacitor such that the rate of change of an output of the operational amplifier is less than a slew rate limit of the operational amplifier.
A method for reducing distortion caused by variations in a threshold voltage of input transistors at an input of an operational amplifier in a switched capacitor circuit including a sampling capacitor, switches for charging the sampling capacitor during a charging phase, and switches for transferring charge from the sampling capacitor to an integration capacitor in a feedback loop of the operational amplifier during a dump phase comprising the step of:
- slowing discharge of the sampling capacitor during the dump phase to minimize transients at the inputs of the input transistors at the input of the operational amplifier by increasing a time constant associated with the sampling capacitor.
A switched capacitor integrator comprising:
- first switches for sampling at least one signal onto at least one sampling capacitor during a first operational phase;
- a operational amplifier including an input summing node;
- an integration capacitor coupling an output of the operational amplifier and the input summing node;
- second switches for transferring charge sampled onto the at least one sampling capacitor to the integration capacitor node during a second operational phase;
- and
- circuitry for reducing a continuous rate of charge transfer between the at least one sampling capacitor and the integration capacitor such that an input of the operational amplifier is maintained in a linear operating range.
Dependencies are inferred from the claim text.