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US 6,617,907 B2Granted
Voltage translator
AssigneeOki Electric Industry Co., Ltd.
InventorYoshihiko Kamata
Life of this patent
Estimating the term…
Abstract
A voltage translator enabling a high speed non-selection switching with regard to the word line voltage. The voltage translator (10) includes one inverter (made up of transistors N1 and P1) arranged on the output side of the voltage transistor circuit, a feedback PMOS type transistor (P2), an NMOS type transistor (N4) having a earth terminal and controlled by the output signal from the other inverter newly added on the input side of the voltage translator circuit, an NMOS type transistor (N3) controlled by the word line, and a PMOS type transistor (P3) controlled by a signal given through an NOMS transistor (N2) connected with the output of the above newly added inverter located on the input side of the voltage translator circuit.
Claims15
A voltage translator supplying either an operation voltage from an operation voltage source or a low voltage from a low voltage source to a word line, in response to a decode signal, comprising:
- an inverter generating a logical selection signal based on said decode signal;
- a first NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with said word line, and a gate electrode connected with the output terminal of said inverter;
- a first PMOS type transistor including a source electrode connected with said operation voltage source, and a drain electrode connected with said word line;
- a second PMOS type transistor including a source electrode connected with the operation voltage source, and a drain electrode connected with the gate of said first PMOS type transistor;
- a second NMOS type transistor including the source electrode connected with the gate electrode of said second PMOS type transistor, a drain electrode connected with said operation voltage source, and a gate electrode connected with said word line;
- a third PMOS type transistor including a source electrode connected with the gate electrode of said second PMOS type transistor and also with the source electrode of said third NMOS transistor, a drain electrode connected with said word line, and a gate electrode connected with the gate electrode of said first PMOS type transistor;
- and
- a third NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with the gate electrode of said second PMOS type transistor, and a gate electrode connected with the output terminal of said inverter.
5 more elements
A voltage translator supplying either an operation voltage from an operation voltage source or a low voltage from a low voltage source to a word line, in response to a decode signal, comprising:
- an inverter generating a logical selection signal based on said decode signal;
- a first NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with said word line, and a gate electrode connected with the output terminal of said inverter;
- a first PMOS type;
- transistor including a source electrode connected with said operation voltage source, and a drain electrode connected with said word line;
- a second NMOS type transistor including a source electrode connected with the output terminal of said inverter, a drain electrode connected with gate electrode of said first PMOS type transistor, and a gate electrode connected with a logical control voltage source;
- a second PMOS type transistor including a source electrode connected with said operation voltage source, and a drain electrode connected with the gate of said first PMOS type transistor;
- a third NMOS type transistor including a source electrode connected with the gate electrode of said second PMOS type transistor, a drain electrode connected with said operation voltage source, and a gate electrode connected with said word line;
- a third PMOS type transistor including a source electrode connected with the gate electrode of said second PMOS type transistor and also with the source electrode of said third NMOS transistor, a drain electrode connected with said word line, and a gate electrode connected with the gate electrode of said first PMOS type transistor;
- and
- a fourth NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with the gate electrode of said second PMOS type transistor, and a gate electrode connected with the output terminal of said inverter.
7 more elements
A voltage translator supplying either an operation voltage from an operation voltage source or an low voltage from a low voltage source to a word line, in response to a decode signal, comprising:
- an inverter generating a logical selection signal based on said decode signal;
- a first NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with said word line, arid a gate electrode connected with the output terminal of said inverter;
- a first PMOS type transistor including a source electrode connected with said operation voltage source, and a drain electrode connected with said word line;
- a second NMOS type transistor including a source electrode connected with the output terminal of said inverter, a drain electrode connected with gate electrode of said first PMOS type transistor, and a gate electrode connected with a logical control voltage source;
- a second PMOS type transistor including a source electrode connected with said operation voltage source, and a drain electrode connected with the gate of said first PMOS type transistor;
- a third NMOS type transistor including a source electrode connected with the gate electrode of said second PMOS type transistor, a drain electrode connected with said word line, and a gate electrode connected with said word line;
- a third PMOS type transistor including a source electrode connected with the gate electrode of said second PMOS type transistor and also with the source electrode of said third NMOS transistor, a drain electrode connected with said word line, and a gate electrode connected with the gate electrode of said first PMOS type transistor;
- and
- a fourth NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with the gate electrode of said second PMOS type transistor, and a gate electrode connected with the output terminal of said inverter.
6 more elements
A voltage translator supplying either an operation voltage from an operation voltage source or a low voltage from a low voltage source to a word line, in response to a decode signal, comprising:
- an inverter generating a logical selection signal based on said decode signal;
- a first NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with said word line, and a gate electrode connected with the output terminal of said inverter;
- a first PMOS type transistor including a source electrode connected with said operation voltage source, and a drain electrode connected with said word line;
- a second PMOS type transistor including a source electrode connected with the operation voltage source, and a drain electrode connected with the gate of said first PMOS type transistor;
- a control circuit which controls a conduction state of said second PMOS type transistor in response to a voltage on said word line, wherein the control circuit includes a third NMOS transistor;
- a third PMOS type transistor including a source electrode connected with the gate electrode of said second PMOS type transistor and also with the source electrode of said third NMOS transistor, a drain electrode connected with said word line, and a gate electrode connected with the gate electrode of said first PMOS type transistor, and
- a fourth NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with the gate electrode of said second PMOS type transistor, and a gate electrode connected with the output terminal of said inverter.
4 more elements
A voltage translator supplying either an operation voltage from an operation voltage source or a low voltage from a low voltage source to a word line, in response to a decode signal, comprising:
- an inverter generating a logical selection signal based on the decode signal;
- a first NMOS type transistor including a source electrode connected with the low voltage source, a drain electrode a drain electrode connected with the word line, and a gate electrode connected with an output terminal of said inverter;
- a first PMOS type transistor including a source electrode connected with the operation voltage source, and a drain electrode connected with the word line;
- a second PMOS type transistor including a source electrode connected with the operation voltage source, and a drain electrode connected with a gate of said first PMOS type transistor;
- a second NMOS type transistor including a source electrode connected with a gate electrode of said second PMOS type transistor, a drain electrode connected with the word line, and a gate electrode connected with the word line;
- a third PMOS type transistor including a source electrode connected with said gate electrode of said second PMOS type transistor and also with said source electrode of said second NMOS type transistor, a drain electrode connected with the word line, and a gate electrode connected with said gate electrode of said first PMOS type transistor;
- and
- a third NMOS type transistor including a source electrode connected with the low voltage source, a drain electrode connected with said gate electrode of said second PMOS type transistor, and a gate electrode connected with said output terminal of said inverter.
5 more elements
Dependencies are inferred from the claim text.