Electronic circuit with clock generating circuit
AssigneeKoninklijke Philips Electronics N.V.
InventorsPatrik Schwarz, Stefan Studerus
Life of this patent
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Abstract
An electronic circuit has a clock input for receiving an input clock signal. A clock processing circuit derives derived clock signals from the input clock signal, for example by frequency dividing the input clock signal. A dual edge triggered sampling circuit samples the derived clock signals at both rising and falling edges of the input clock signal. The sampled clocks are thus synchronized and are used to control operation of processing circuitry.
Claims6
An electronic circuit comprising a clock derivation circuit having
- a clock input for receiving an input clock signal,
- a clock processing circuit coupled to the clock input for deriving a derived clock signal from the input clock signal,
- a plurality of dual edge triggered sampling circuits each with a signal input coupled to an output of the clock processing circuit and a sampling clock input coupled to the clock input, for sampling the derived clock signal at both rising and falling edges of the input clock signal, and wherein each of the plurality of dual edge triggered sampling circuits have an output coupled directly to a clocked circuit, and each of the plurality of dual edge triggered sampling circuits have an input coupled to a respective output of the clock processing circuit,
- wherein the value of the derived clock signal is captured at both edges of the input clock signal, and wherein the sampled result goes high at an edge of the input clock signal when the derived clock signal is high and goes low at an edge of the input clock signal when, the derived clock signal is low.
An electronic circuit comprising a clock derivation circuit having
- a clock input for receiving an input clock signal,
- a clock processing circuit coupled to the clock input for deriving a derived clock signal from the input clock signal,
- a plurality of dual edge triggered sampling circuits each with a signal input coupled to an output of the clock processing circuit and a sampling clock input coupled to the clock input, for sapling the derived clock signal at both rising and falling edges of the input clock signal, and wherein each of the plurality of dual edge triggered sampling circuits have an output coupled directly to a clocked circuit, and each of the plurality of dual edge triggered sampling circuits have an input coupled to a respective output of the clock processing circuit,
- wherein a frequency of the derived clock signal produced by the clock processing circuit is equal to a frequency of the input clock signal.
An electronic circuit comprising a clock derivation circuit having
- a clock input for receiving an input clock signal,
- a clock processing circuit coupled to the clock input for deriving a derived clock signal from the input clock signal,
- a plurality of dual edge triggered sampling circuits each with a signal input coupled to an output of the clock processing circuit and a sampling clock input coupled to the clock input, for sampling the derived clock signal at both rising and falling edges of the input clock signal, and wherein each of the plurality of dual edge triggered sampling circuits have an output coupled directly to a clocked circuit, and each of the plurality of dual edge triggered sampling circuits have an input coupled to a respective output of the clock processing circuit,
- wherein all sampled derived clock signals have a leading edge that is synchronized with an edge of the input clock signal.
Dependencies are inferred from the claim text.