Semiconductor memory and holding device

A semiconductor holding device using a first power source and a second power source, comprising:

• a clock generator configured to generate a clock signal;
• a delay block including an odd number of inverter elements, the clock signal being supplied to the delay block to generate a delay clock signal of the same swing as the clock signal;
• a first transistor circuit including a P type first transistor connected to the first power source, an N type second transistor connected to the first transistor, an N type third transistor connected to the second transistor and an N type fourth transistor connected between the third transistor and the second power source;
• and
• a second transistor circuit including a P type fifth transistor connected to the first power source, an N type sixth transistor connected to the fifth transistor, an N type seventh transistor connected to the sixth transistor, and an N type eighth transistor connected between the seventh transistor and the second power source, an input signal being supplied to gates of the N type second and sixth transistors, the delay clock signal being supplied to gates of only the fourth and eighth transistors, a node of the first and second transistors being connected to gates of the fifth and the seventh transistors and a node of the fifth and sixth transistors serving as an output node,
• wherein the clock signal is not supplied to any P type transistor.