Master/dual-slave D type flip-flop
AssigneeCypress Semiconductor Corporation
InventorJay A. Kuhn
Life of this patent
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Abstract
An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to receive a first input signal and a second input signal and present a first signal and a second signal. The second circuit may be configured to present a first output signal in response to the first input signal, the first signal and the second signal. The third circuit may be configured to present a second output signal in response to the second input signal, the first signal and the second signal.
Claims18
An apparatus comprising:
- a first circuit configured to receive a first input signal and a second input signal and present a first signal and a second signal;
- a second circuit (i) comprising a first slave latch and a first transfer latch (ii) configured to present a first output signal in response to said first input signal, said first signal and said second signal;
- and
- a third circuit (i) comprising a second slave latch and a second transfer latch (ii) configured to present a second output signal in response to said second input signal, said first signal and said second signal.
A method for providing a master/dual-slave flip-flop, comprising the steps of:
- (A) presenting a first signal and a second signal in response to a first input signal and a second input signal;
- (B) presenting a first output signal using a first slave latch and a first transfer latch, in response to said first input signal, said first signal and said second signal;
- and
- (C) presenting a second output signal using a second slave latch and a second transfer latch, in response to said second input signal, said first signal and said second signal.
An apparatus comprising:
- a first circuit configured to receive a first input signal and a second input signal and present a first signal and a second signal;
- a second circuit configured to present a first output signal in response to said first input signal, said first signal and said second signal;
- and
- a third circuit configured to present a second output signal in response to said second input signal, said first signal and said second signal, wherein said first output signal comprises a complementary output pair and said second output signal comprises a complementary output pair.
Dependencies are inferred from the claim text.