Ultra high speed clocked analog latch
AssigneeInfineon Technologies AG
InventorSasan Cyrusian
Life of this patent
Estimating the term…
Abstract
An ultra high-speed clocked analog latch is revealed for use at clock speeds from 100 MHz to several GHz. The analog latch is used as a latching comparator for comparing a time-varying analog signal with an analog reference voltage. The latch uses CMOS manufacturing technology and a minimal amount of space for a two-stage amplifying and signal-generating device. The latch is useful in analog to digital converters (ADCs) in which high speed and high reliability are required, but only a small amount of space is available. The device is so small and economical that several may be used in series to avoid any meta-stability problems in high-speed read/write operations.
Claims32
An analog latch, comprising:
- a first preamplifier and a second preamplifier, series connected and receiving a differential voltage signal and acting to amplify the differential voltage signal, and to output the differential voltage signal;
- at least one differential clocked analog latch stage, the at least one differential clocked analog latch stage comprising no more than six transistors, receiving the differential voltage signal from the first and second preamplifiers and producing a high signal or a low signal dependent on the differential voltage signal received,
- an RS latch, connected in series to the at least one differential analog latch stage, receiving and holding the high signal or low signal from the at least one analog latch stage, and
- a clock generator, producing control signals for the first preamplifier, the second preamplifier, and the at least one analog latch stage,
- wherein the clock generator generates control signals for the first preamplifier, the second preamplifier, and the at least one analog latch stage, the control signals including timing signals, autozero signals and reset signals.
An analog latch circuit, comprising:
- at least one differential clocked analog latch stage, the at least one differential clocked analog latch stage comprising no more than six transistors, producing an output high or low signal in response to an input signal;
- an RS latch receiving a high or low signal from the at least one analog latch stage;
- a clock generator, wherein the clock generator produces control signals for the at least one analog latch stage, and
- a first preamplifier, the preamplifier receiving and amplifying an input signal, and producing an output signal for the at least one differential clocked analog latch stage, and wherein the clock generator produces control signals for the first preamplifier.
An analog latch circuit, comprising:
- at least one differential clocked analog latch stage, wherein the analog latch stage comprises six transistors only;
- an RS latch receiving a high or low signal from the at least one analog latch stage;
- a clock generator, wherein the clock generator produces control signals for the at least one analog latch stage;
- a first preamplifier, the preamplifier receiving and amplifying an input signal, and producing an output signal for the at least one differential clocked analog latch stage;
- and
- a second preamplifier connected between the first preamplifier and the at least one differential clocked analog latch stage.
An analog latch, comprising:
- a first preamplifier and a second preamplifier, series connected and receiving a differential voltage signal and acting to amplify the differential voltage signal;
- at least one differential clocked analog latch stage, the at least one differential clocked analog latch stage comprising no more than six transistors, connected in series with the second amplifier;
- an RS latch, connected in series to the at least one differential analog latch stage;
- and
- a clock generator, producing control signals for the first preamplifier, the second preamplifier.
Dependencies are inferred from the claim text.