Circuits and methods for generating internal clock signal of intermediate phase relative to external clock

A circuit comprising:

• a clock buffer to generate an initial reference clock signal responsive to an external clock signal;
• a delay monitoring circuit (DMC) to receive the initial reference clock signal;
• an array of forward units arranged in a plurality of stages to receive a signal from the DMC;
• an array of back units;
• a clock driver to produce an internal clock signal in response to a back signal received from one of the back units;
• a standalone delay element to produce a delayed reference signal responsive to the initial reference clock signal, wherein the standalone delay element includes a plurality of intermediate delay units corresponding individually to at least some of the stages of the forward units;
• and
• a plurality of mirror control circuits (MCCs), each MCC receiving an output of one of the forward units and the delayed reference clock signal,
• wherein when one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated to initiate generation of the back signal.