US 6,617,893 B1 · Digital variable clock divider

Abstract

A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider. The single phase slip divider of the second embodiment may be configured to stay or shift on each phase of the clock in that consecutive phases may be merged or may remain distinct in the output signal of the phase slip non-integral divider portion of the circuit. The output of the phase slip divider of the second embodiment is then applied to an integral divider portion to produce the final output clock signal. Both embodiments provide for integral and non-integral division of a multi-phase input clock signal. The first embodiment provides for additional flexibility at the expense of added complexity relative to the first embodiment.

Claims20

Dependent claims

A clock divider circuit comprising:

an integral divider portion for dividing a source input clock signal by an integral divisor to produce a divided clock signal;
and
a phase slip portion for applying a predetermined phase slip to said divided clock signal to produce a phase slipped divided clock signal as a non-integral division of said source input clock signal.

A clock divider circuit comprising:

a multi-phase frequency synthesizer which generates a plurality of source input clock signals at a predetermined base frequency wherein said plurality of source input clock signals have a predetermined phase relationship;
a plurality of phase slip dividers wherein each of said plurality of phase slip dividers is associated with a unique one of said plurality of source input clock signals generated by said multi-phase frequency synthesizer and wherein each of said plurality of phase slip dividers controllably slips its associated source input clock signal by a predetermined phase offset to produce an output signal;
and
control means for selectively combining said output signal of each of said plurality of phase slip dividers to generate a final output clock signal.

1 more element

Dependencies are inferred from the claim text.

Digital variable clock divider

Life of this patent

Digital variable clock divider

Life of this patent

Abstract

Claims20