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US 6,617,885 B2Granted
Sense amplifiers having gain control circuits therein that inhibit signal oscillations
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-hyoung Lim, Kyoung-woo Kang, Dong-ho Hyun
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Abstract
Integrated circuit memory devices according to the present invention include a sense amplifier having a pair of differential input signal lines, a pair of differential output signal lines, and a current amplifier. The current amplifier has an input stage electrically coupled to the pair of differential input signal lines and an output stage electrically coupled to the pair of differential output signal lines. The input stage and/or the output stage are responsive to a first control signal that reduces a gain of the current amplifier when the first control signal is asserted.
Claims11
A sense amplifier integrated circuit, comprising:
- pair of differential input signal lines and a pair of differential output signal lines;
- and
- a current amplifier having an input stage electrically coupled to said pair of differential input signal lines and art output stage electrically coupled to said pair of differential output signal lines, said input stage or said output stage responsive to a first control signal that reduces a gain of said current amplifier when the first control signal is asserted, wherein said input stage comprises:
- a load circuit that is electrically coupled to said pair of differential input signal lines and a first reference signal line, wherein said load circuit is responsive to the first control signal and a second control signal;
- and wherein during a sense and amplify time interval, an impedance of a load provided by said load circuit to said pair of differential input signal lines increases from a first level when the second control signal is being asserted and the first control signal is not being asserted to a second level higher than the first level when the first and second control signals are both being asserted.
2 more elements
A sense amplifier integrated circuit, comprising:
- a pair of differential input signal lines and a pair of differential output signal lines;
- and
- a current amplifier having an input stage electrically coupled to said pair of differential input signal lines and an output stage electrically coupled to said pair of differential output signal lines, said output stage responsive to a first control signal tat reduces a gain of said current amplifier when the first control signal is asserted, wherein said output stage comprises:
- a stabilizer circuit that is electrically coupled to said pair of differential output signal lines, wherein said stabilizer circuit is responsive to the first control signal;
- and wherein during a sense and amplify time interval, an impedance of a load provided by said stabilizer circuit to said pair of differential output signal lines increases from a first level when the first control signal is not being asserted to a second level when the first control signal is being asserted.
2 more elements
An output data amplifier of a semiconductor device comprising:
- a pair of input data lines;
- a current input amplifying unit for sensing and amplifying a level difference between signals on the pair of input data lines and outputting a result as a voltage level;
- and
- a latch amplifying unit for sensing the voltage level output from the current input amplifying unit and amplifying the voltage level to a level sufficient to be transmitted to a peripheral circuit,
- wherein a gain of the current input amplifying unit during a first portion of a sense and amplify time interval is different from the gain of the current input amplifying unit during a second portion of the sense and amplify time interval.
2 more elements
An output data amplifier of a semiconductor device comprising:
- a pair of input data lines;
- a current input amplifying unit for sensing and amplifying a level difference between signals on the pair of input data lines and outputting a result as a voltage level;
- and
- a latch amplifying unit for sensing the voltage level output from the current input amplifying unit and amplifying the voltage level to a level sufficient to be transmitted to a peripheral circuit,
- wherein the current input amplifying unit comprises a load circuit for controlling an amount of current flowing through the current input amplifying unit, and
- wherein a load of the load circuit during a first portion of a sense and amplify time interval is different from the load of the load circuit during a second portion of the sense and amplify time interval.
3 more elements
An output data amplifier of a semiconductor device comprising:
- a pair of input data lines;
- a current input amplifying unit for sensing and amplifying the level difference between signals on the pair of input data lines and outputting the result as a voltage level;
- and
- a latch amplifying unit for sensing the voltage level output from the current input amplifying unit and amplifying the voltage level to a level sufficient to be transmitted to a peripheral circuit,
- wherein the current input amplifying unit comprises an output voltage stabilizing circuit for limiting the voltage level output from the current input amplifying unit, wherein the output voltage stabilizing circuit is a MOS transistor having a drain connected to one of output nodes of the current input amplifying unit and the source connected to the other node, which is gated by a control signal, and
- wherein a signal, which is activated when a predetermined period of time lapses after a column select disable signal for disabling a column select signal is activated, and is automatically deactivated when a predetermined period of time lapses after having been activated, is used as the control signal.
3 more elements
Dependencies are inferred from the claim text.