Fast locking phase frequency detector
AssigneeAltera Corporation
InventorsXiaobao Wang, Chiakang Sung, Joseph Huang, Bonnie I. Wang, Khai Nguyen, Wayne Yeung, In Whan Kim
Life of this patent
Estimating the term…
Abstract
A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.
Claims33
A circuit comprising:
- a first register having a first data input, a first clock input coupled to a first clock signal, and a first data output;
- a second register having a second data input coupled to the first data output, a second clock input coupled to the first clock signal, and a second data output;
- a third register having a third data input, a third clock input coupled to a second clock signal, and a third data output;
- a fourth register having a fourth data input coupled to the third data output, a fourth clock input coupled to the second clock signal, and a fourth data output;
- a first logic gate, coupled to the first and third data outputs, having a first logic output coupled to a first clear input of the first register;
- and
- a second logic gate, coupled to the second and third data outputs, having a second logic output coupled to a second clear input of the second register.
A method of maintaining a phase relationship between a first clock signal and a second clock signal comprising:
- providing a first UP output and a second UP output;
- generating a pulse at the first UP output when a first edge of the first clock signal leads a first edge of the second clock signal;
- and
- generating a pulse at the second UP output when a second edge of the first clock signal leads the first edge of the second clock signal,
- wherein one pulse is generated at either the first UP output or the second UP output at a time.
A method of maintaining a phase relationship between a first clock signal and a second clock signal comprising:
- providing a first UP output and a second UP output;
- generating a pulse at the first UP output when a first edge of the first clock signal leads a first edge of the second clock signal;
- generating a pulse at the second UP output when a second edge of the first clock signal leads the first edge of the second clock signal;
- and
- making pulses generated at the first UP output and the second UP output having the same pulse width.
A method of maintaining a phase relationship between a first clock signal and a second clock signal comprising:
- providing a first DOWN output and a second DOWN output;
- generating a pulse at the first DOWN output when a first edge of the first clock signal leads a first edge of the second clock signal;
- and
- generating a pulse at the second DOWN output when a second edge of the first clock signal leads the first edge of the second clock signal,
- wherein one pulse is generated at either the first DOWN output or the second DOWN output at a time.
A method of maintaining a phase relationship between a first clock signal and a second clock signal comprising:
- providing a first DOWN output and a second DOWN output;
- generating a pulse at the first DOWN output when a first edge of the first clock signal leads a first edge of the second clock signal;
- generating a pulse at the second DOWN output when a second edge of the first clock signal leads the first edge of the second clock signal;
- and
- making pulses generated at the first DOWN output and the second DOWN output having the same pulse width.
A method of maintaining a phase relationship between a first clock signal and a second clock signal comprising:
- providing a first UP output, a second UP output, a first DOWN output, and a second DOWN output;
- starting in an initial state;
- transitioning to a first UP state and generating a pulse at the first UP output when a first edge of the first clock signal leads a first edge of the second clock signal;
- transitioning to a second UP state and generating a pulse at the second UP output when a second edge of the first clock signal leads the first edge of the second clock signal;
- transitioning to a first DOWN state and generating a pulse at the first DOWN output when a third edge of the first clock signal lags a third edge of the second clock signal;
- and
- transitioning to a second DOWN state and generating a pulse at the second DOWN output when a fourth edge of the first clock signal lags the third edge of the second clock signal,
- wherein one pulse is generated at either the first UP output or the second UP output at a time.
Dependencies are inferred from the claim text.