Dual differential input comparators with integrated phase detector
AssigneeCypress Semiconductor Corporation
InventorJay A. Kuhn
Life of this patent
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first intermediate signal in response to a first differential signal and (ii) a second intermediate signal in response to a second differential signal. The second circuit may be configured (i) to generate one or more output signals in response to a relative arrival time of the first and second intermediate signals and (ii) to clamp a later arriving one of the first and second intermediate signals to a predefined voltage level.
Claims20
An apparatus comprising:
- a first circuit configured to generate (i) a first intermediate signal in response to a first differential signal and (ii) a second intermediate signal in response to a second differential signal;
- and
- a second circuit configured (i) to generate one or more output signals in response to a relative arrival time of said first and second intermediate signals and (ii) to clamp a later arriving one of said first and second intermediate signals to a predefined voltage level.
An apparatus comprising:
- means for generating (i) a first intermediate signal in response to a first differential signal and (ii) a second intermediate signal in response to a second differential signal;
- and
- means for generating one or more output signals in response to a relative arrival time of said first and second intermediate signals and clamping a later arriving one of said intermediate signals to a predefined voltage level.
A method for generating an output signal indicative of which of two differential signals arrives first comprising the steps of:
- generating a first intermediate signal in response to a first differential signal;
- generating a second intermediate signal in response to a second differential signal;
- generating one or more output signals in response to a relative arrival time of said first and second intermediate signals;
- and
- clamping a later arriving one of said first and second intermediate signals to a predefined voltage level.
Dependencies are inferred from the claim text.