Clocked half-rail differential logic
AssigneeSun Microsystems, Inc.
InventorSwee Yew Choe
Life of this patent
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Abstract
Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.
Claims3
A cascaded chain of clocked half-rail differential logic circuits, said chain comprising:
- a first clock d half-rail differential logic circuit, said first clocked half-rail differential logic circuit comprising:
- a first locked half-rail differential logic circuit clock input terminal;
- at least one first clocked half-rail differential logic circuit data input terminal;
- and
- at least one first clocked half-rail differential logic circuit data output terminal;
- a second clocked half-rail differential logic circuit, said second clocked half-rail differential logic circuit comprising:
- a second clocked half-rail differential logic circuit clock input terminal;
- at least one second clocked half-rail differential logic circuit data input terminal;
- and
- at least one second clocked half-rail differential logic circuit data output terminal;
- a third clock d half-rail differential logic circuit, said third clocked half-rail differential logic circuit comprising:
- a third clocked half-rail differential logic circuit lock input terminal;
- at east one third clocked half-rail differential logic circuit data input terminal;
- and
- at east one third clocked half-rail differential logic circuit data output terminal;
- a first clock signal coupled to said first clocked half-rail differential logic circuit clock input terminal;
- a second clock signal coupled to said second clocked half-rail differential logic circuit clock input terminal;
- a third clock signal coupled to said third clocked half-rail differential logic circuit clock input terminal, wherein;
- said at least one first clocked half-rail differential logic circuit data output terminal is coupled to said at least one second clocked half-rail differential logic circuit data input terminal, further wherein;
- said at least one second clocked half-rail differential logic circuit data output terminal is coupled to said at least one third clocked half-rail differential logic circuit data input terminal, further wherein;
- said second lock signal is delayed with respect to said first clock signal by a predetermined delay time, further wherein;
- said third clock signal is delayed with respect to said second clock signal by a predetermined delay time;
- a first delay circuit coupled between said first clocked half-rail differential logic circuit clock input terminal and said second clock d half-rail differential logic circuit clock input terminal for providing said predetermined delay time;
- and
- a second delay circuit coupled between said second clocked half-rail differential logic circuit clock input terminal and said third clocked half-rail differential logic circuit clock input terminal for providing said predetermined delay time.
Dependencies are inferred from the claim text.