Transparently partitioned communication bus for multi-port bridge for a local area network

A multi-port bridge having a partitioned bus for transferring data between ports of the multi-port bridge, the multi-port bridge comprising:

• a. a first bus segment having a first plurality of (n) signal lines;
• b. a second bus segment having a second plurality of (n) signal lines;
• c. a controller coupled to the first bus segment for sensing a logic level of each signal line of the first bus segment;
• d. a transistor coupled to be controlled by the controller for pre-charging each signal line of the second bus segment;
• and
• e. a plurality of transistors coupled to be controlled by the controller for dis-charging selected ones of the signal lines of the second bus segment so as to replicate logic levels of the corresponding signal lines of the first bus segment.

A method of transferring data between ports of a multi-port bridge, the method comprising steps of:

• a. conditioning a first bus segment having a first plurality of (n) signal lines according to logic levels of data to be transferred by a first port;
• b. pre-charging a second bus segment having a second plurality of (n) signal lines whereby each signal line of each of the second bus segment attains a logic high voltage level;
• c. sensing a logic level of each signal line of the first bus segment;
• and
• d. dis-charging selected ones of the signal lines of the second bus segment to a logic low voltage level so as to replicate the logic levels of the first bus segment.

A multi-port bridge having a partitioned bus for transferring data between ports the multi-port bridge, the multi-port bridge comprising:

• a. a first bus segment having a first plurality of (n) signal lines;
• b. a second bus segment having a second plurality of (n) signal lines;
• c. a controller coupled to the first bus segment via a first plurality of (n) sense lines for sensing a respective logic level of each signal line of the first bus segment and coupled to the second bus segment via a second plurality of (n) sense lines for sensing a respective logic level of each signal line of the second bus segment;
• d. a first plurality of diodes, each having an anode and a cathode, wherein the cathodes of the first plurality of diodes are each coupled to a respective one of the signal lines of the first bus segment and the anodes of the first plurality of diodes are each selectively coupled to a supply voltage under control of the controller;
• e. a second plurality of diodes, each having an anode and a cathode, wherein the cathodes of the first plurality of diodes are each coupled to a respective one of the signal lines of the second bus segment and the anodes of the second plurality of diodes are each selectively coupled to a first supply voltage level under control of the controller;
• f. a first plurality of transistors, each having an input terminal, an output terminal and a control terminal, wherein the input terminals of the first plurality of transistors are each coupled to a second supply voltage level, and wherein the output terminals of the first plurality of transistors are each coupled to a respective one of the signal lines of the first bus segment and further wherein the control terminals of the first plurality of transistors are each coupled to the controller;
• and
• g. a second plurality of transistors, each having an input terminal, an output terminal and a control terminal, wherein the input terminals of the second plurality of transistors are each coupled to the second supply voltage level, and wherein the output terminals of the second plurality of transistors are each coupled to a respective one of the signal lines of the second bus segment and further wherein the control terminals of the second plurality of transistors are each coupled to the controller.