Variable data width operation in multi-gigabit transceivers on a programmable logic device

A method of operating a programmable logic device including configurable core logic, a multi-gigabit transceiver, and a variable-width interface circuit, the method comprising:

• configuring the core logic to have a transmit port coupled to the variable-width interface circuit, wherein the transmit port is selected to have a first width that is selected from a plurality of widths;
• routing data values having the first width from the core logic to the variable-width interface circuit on the transmit port in response to a first clock signal;
• converting the data values having the first width to data values having a second width using the variable-width interface circuit;
• and
• routing data values having the second width from the variable-width interface circuit to the multi-gigabit transceiver in response to a second clock signal.

A method of operating a programmable logic device including configurable core logic, a multi-gigabit transceiver, and a variable-width interface circuit, the method comprising:

• routing data values having a first width from the multi-gigabit transceiver to the variable-width interface circuit in response to a first clock signal;
• converting the data values having the first width to data values having a second width, which is selected from a plurality of widths, using the variable-width interface circuit;
• configuring the core logic to have a receive port coupled to the variable-width interface circuit, wherein the receive port is selected to have the second width;
• routing data values having the second width from the variable-width interface circuit to the core logic on the receive port in response to a second clock signal.

A system, comprising:

• a clock source having an output clock terminal;
• an integrated circuit (IC), the IC comprising:
• a first clock input terminal coupled to the output clock terminal of the clock source;
• a multi-gigabit transceiver circuit (MGT) having a fixed width;
• a core logic block;
• and
• a variable width interface circuit (VWIF) coupled between the MGT and the core logic block, the VWIF having a first clock input terminal coupled to the first clock input terminal of the IC.