Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers
AssigneeXilinx, Inc.
InventorGoran Bilski
Life of this patent
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Abstract
Structures and methods that reduce interconnect resource usage and routing delays in FPGAs by routing high fan-out signals on the CLB carry chains. In a first embodiment, a high fan-out signal distribution structure is implemented in a Field Programmable Gate Array (FPGA). The FPGA includes an array of logic cells, each including a carry multiplexer. The carry multiplexers can be configured to form a carry chain. The carry chain is used to distribute high fan-out signals by passing a high fan-out signal along the chain from carry-in terminal to carry-out terminal, and tapping the signal at the carry-out terminals for distribution to a large number of destinations.
Claims23
A high fan-out signal distribution structure implemented in a Field Programmable Gate Array (FPGA), the FPGA comprising a plurality of carry multiplexers in associated logic cells and an interconnect structure interconnecting the logic cells, the structure comprising:
- a high fan-out input terminal;
- a first carry multiplexer in a first logic cell, the first carry multiplexer having a carry-out terminal, a carry-in terminal coupled to the high fan-out input terminal, and a select terminal selecting a signal on the carry-in terminal for placement on the carry-out terminal;
- a second carry multiplexer in a second logic cell, the second carry multiplexer having a carry-out terminal, a carry-in terminal coupled to the carry-out terminal of the first carry multiplexer, and a select terminal selecting a signal on the carry-in terminal for placement on the carry-out terminal;
- a first portion of the interconnect structure coupled between the carry-out terminal of the first carry multiplexer and at least a first destination and completing an interconnection therebetween;
- and
- a second portion of the interconnect structure coupled between the carry-out terminal of the second carry multiplexer and at least a second destination and completing an interconnection therebetween.
A method for distributing a high fan-out signal in a Field Programmable Gate Array (FPGA) comprising logic cells and an interconnect structure interconnecting the logic cells, the method comprising:
- configuring a first carry multiplexer in a first logic cell to accept the high fan-out signal and to pass the high fan-out signal to a first carry multiplexer output terminal as a first carry-out signal;
- configuring a second carry multiplexer in a second logic cell to accept the first carry-out signal and to pass the accepted signal to a second carry multiplexer output terminal as a second carry-out signal;
- configuring the interconnect structure to pass the first carry-out signal to at least a first destination;
- and
- configuring the interconnect structure to pass the second carry-out signal to at least a second destination.
A high fan-out signal distribution structure implemented in a Field Programmable Gate Array (FPGA), the FPGA comprising a plurality of carry multiplexers in associated logic cells and an interconnect structure interconnecting the logic cells, the structure comprising:
- means for configuring a first carry multiplexer in a first logic cell to accept a high fan-out signal and to pass the high fan-out signal to a first carry multiplexer output terminal as a first carry-out signal;
- means for configuring a second carry multiplexer in a second logic cell to accept the first carry-out signal and to pass the accepted signal to a second carry multiplexer output terminal as a second carry-out signal;
- means for configuring the interconnect structure to pass the first carry-out signal to at least a first destination;
- and
- means for configuring the interconnect structure to pass the second carry-out signal to at least a second destination.
A computer storage device comprising configuration data to configure a Field Programmable Gate Array (FPGA) comprising logic cells and an interconnect structure interconnecting the logic cell, the configuration data comprising:
- a first set of the configuration data that configures a first carry multiplexer in a first logic cell to accept the high fan-out signal and to pass the high fan-out signal to a first carry multiplexer output terminal as a first carry-out signal;
- a second set of the configuration data that configures a second carry multiplexer in a second logic cell to accept the first carry-out signal and to pass the accepted signal to a second carry multiplexer output terminal as a second carry-out signal;
- a third set of the configuration data that configures the interconnect structure to pass the first carry-out signal to at least a first destination;
- and
- a fourth set of the configuration data that configures the interconnect structure to pass the second carry-out signal to at least a second destination.
Dependencies are inferred from the claim text.