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US 6,617,875 B2Granted
Programmable multi-standard I/O architecture for FPGAs
AssigneeActel Corporation
InventorKhaled A. El-Ayat
Life of this patent
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Abstract
The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards.
Claims3
A programmable antifuse matrix cell comprising:
- A two terminal antifuse
- An N-channel transistor
- A p-channel transistor
- One terminal of said antifuse connected to a first source/drain terminal of said N-channel transistor and to a first source/drain terminal of said P-channel transistor and to an output node
- Second terminal of said antifuse connected to ground
- The gates of two said transistors are connected
- The second source/drain terminal of said N-channel transistor is connected to a first voltage
- Second source/drain terminal of said P-channel transistor is connected to a second voltage.
5 more elements
Dependencies are inferred from the claim text.