Power-up logic reference circuit and related method

An apparatus comprising:

• a power-up sensing circuit to generate a signal in response to said power-up sensing circuit being powered up;
• and
• a latch circuit to generate and sustain a known reference voltage in response to said signal, wherein said power-up sensing circuit comprises:
• a first p-channel field effect transistor (FET) including a first source, a first drain, and a first gate, wherein said first source is connected to a first voltage rail and said first gate is connected to said latch circuit;
• a first n-channel field effect transistor (FET) including a second source, a second drain, and a second gate, said second source being connected to a second voltage rail, said second gate being connected to said latch circuit and to said first drain of said first p-channel FET, and said second drain being connected to said gate of said first p-channel FET;
• and
• a voltage offsetting device connected between said first drain of said first p-channel FET and said second drain of said first n-channel FET.

An apparatus comprising:

• a power-up sensing circuit to generate a signal in response to said power-up sensing circuit being powered up;
• and
• a latch circuit to generate and sustain a known reference voltage in response to said signal, wherein said latch circuit comprises:
• a first p-channel FET including a first source, a first drain, and a first gate, said first source being connected to a first voltage rail;
• a first n-channel FET including a second source, a second drain, and a second gate, said second source being connected to a second voltage rail, said second drain being connected to said first drain of said first p-channel FET, and said second gate connected to said first gate of said first p-channel FET;
• a second p-channel FET including a third source, a third drain, and a third gate, said third source being connected to said first voltage rail, said third drain being connected to said first and second gates of respectively said first p-channel FET and said first n-channel FET, and to said power-up sensing circuit;
• and
• a second n-channel FET including a fourth source, a fourth drain, and a fourth gate, said fourth source being connected to said second voltage rail, said fourth drain being coupled to said third drain of said second p-channel FET, to said first and second gates of respectively said first p-channel FET and said first n-channel FET, and to said power-up sensing circuit, and said fourth gate being connected to said third gate of said second p-channel FET, to said first and second drains of respectively said first p-channel FET and said first n-channel FET, and to said power-up sensing circuit.

A circuit comprising:

• a power-up sensing circuit to generate a set signal in response to said power-up sensing circuit being powered up;
• a latch circuit to generate a reference logic level voltage and an inverted reference logic voltage in response to said set signal;
• and
• a logic circuit to use said reference logic level voltage and/or said inverted reference logic voltage, wherein said inverter comprises:
• a first p-channel field effect transistor (FET) including a first source, a first drain, and a first gate, said first source coupled to a first voltage rail and said first gate coupled to said latch circuit to receive said reference logic level voltage;
• a second p-channel field effect transistor (FET) including a second source, a second drain, and a second gate, said second source connected to said first drain of said first p-channel FET;
• a first n-channel field effect transistor (FET) including a third source, a third drain, and a third gate, said third drain coupled to said second drain of said second p-channel transistor and serving as an output for said inverter, and said third gate coupled to said second gate of said second p-channel FET and serving as an input for said inverter;
• and
• a second n-channel field effect transistor (FET) including a fourth source, a fourth drain, and a fourth gate, said fourth source connected to a second voltage rail, said fourth drain coupled to said third source of said first n-channel FET, and said fourth gate connected to said latch circuit to receive said inverted reference logic level voltage.

A method comprising:

• providing a power-up sensing circuit to generate a set signal in response to an activation of a power supply voltage;
• setting a latch using said set signal to generate a reference voltage;
• and
• resetting said latch and reducing a power consumption of said power-up sensing circuit in response to a reset signal.

A circuit comprising:

• a power-up sensing circuit to generate a set signal in response to said power-up sensing circuit being powered up;
• a latch circuit to generate a reference logic level voltage and an inverted reference logic voltage in response to said set signal;
• and
• a logic circuit to use said reference logic level voltage and/or said inverted reference logic voltage, wherein said latch circuit comprises:
• a first p-channel FET including a first source, a first drain, and a first gate, said first source being connected to a first voltage rail;
• a first n-channel FET including a second source, a second drain, and a second gate, said second source being connected to a second voltage rail, said second drain being connected to said first drain of said first p-channel FET, and said second gate being connected to said first gate of said first p-channel FET;
• a second p-channel FET including a third source, a third drain, and a third gate, said third source being connected to said first voltage rail, said third drain being connected to said first and second gates of respectively said first p-channel FET and said first n-channel FET, and to said power-up sensing circuit;
• and
• a second n-channel FET including a fourth source, a fourth drain, and a fourth gate, said fourth source being connected to said second voltage rail, said fourth drain connected to said third drain of said second p-channel FET, to said first and second gates of respectively said first p-channel FET and said first n-channel FET, and to said power-up sensing circuit, and said fourth gate connected to said third gate of said second p-channel FET, to said first and second drains of respectively said first p-channel FET and said first n-channel FET, and to said power-up sensing circuit.

A circuit, comprising:

• a power-up sensing circuit to generate a set signal in response to said power-up sensing circuit being powered up;
• a latch circuit to generate a reference logic level voltage and an inverted reference logic voltage in response to said set signal;
• and
• a decoder circuit to cause a reduction in a power consumption of said power-up circuit and said latch circuit in response to a reset signal;
• and
• a logic circuit to use said reference logic level voltage and/or said inverted reference logic voltage.

A circuit comprising:

• a power-up sensing circuit to generate a set signal in response to said power-up sensing circuit being powered up;
• a latch circuit to generate a reference logic level voltage and an inverted reference logic voltage in response to said set signal;
• and
• a logic circuit to use said reference logic level voltage and/or said inverted reference logic voltage, wherein said power-up sensing circuit comprises:
• a first p-channel field effect transistor (FET) including a first source, a first drain, and a first gate, wherein said first source is coupled to a first voltage rail and said first gate is connected to said latch circuit;
• a first n-channel field effect transistor (FET) including a second source, a second drain, and a second gate, said second source being connected to a second voltage rail, said second gate being connected to said latch circuit and to said first drain of said first p-channel FET, and said second drain being coupled to said first gate of said first p-channel FET;
• and
• a voltage offsetting device connected between said first drain of said first p-channel FET and said second drain of said first n-channel FET.