Reduced cost, high speed integrated circuit test arrangement
AssigneeTexas Instruments Incorporated
InventorWilbur C. Vogley
Life of this patent
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Abstract
An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.
Claims17
A method of testing comprising the steps of:
- selecting a test algorithm at a control computer;
- sending the test algorithm to a first plurality of integrated circuits;
- executing the test algorithm at each of the plurality of integrated circuits;
- producing a plurality of respective test signals at each integrated circuit of the first plurality of integrated circuits corresponding to the test algorithm;
- applying the plurality of respective test signals to a respective second plurality of integrated circuits to be tested;
- and
- testing each integrated circuit of the second plurality of integrated circuits in response to the plurality of respective test signals.
A method comprising the steps of:
- selecting an algorithm at a control computer;
- sending the algorithm to a plurality of integrated circuits;
- executing the algorithm at each of the plurality of integrated circuits;
- producing a plurality of respective address, data, and control signals at each integrated circuit corresponding to the algorithm, wherein the address signals include row and column address signals, and wherein the control signals include row and column control signals;
- and
- applying the plurality of respective signals to respective operating circuits.
A method comprising the steps of:
- selecting an algorithm at a control computer;
- sending the algorithm to a plurality of integrated circuits;
- sending the algorithm to the plurality of integrated circuits on a serial bus;
- executing the algorithm at each of the plurality of integrated circuits;
- producing a plurality of respective signals at each integrated circuit corresponding to the algorithm;
- applying the plurality of respective signals to respective operating circuits;
- and
- receiving respective data on the serial bus from each of said operating circuits, wherein the steps of sending and receiving correspond to a scalable coherent interface standard.
Dependencies are inferred from the claim text.