Method and apparatus for characterization of electronic circuitry
AssigneeSun Microsystems, Inc.
InventorHemavann Thao
Life of this patent
Estimating the term…
Loading patent…
AssigneeSun Microsystems, Inc.
InventorHemavann Thao
Estimating the term…
The present invention is a method and apparatus for characterization of electronic circuitry. Electronic systems rely on correct circuitry to function properly. Thus, a testing process is utilized to ensure correctness of circuitry. Some testing methods require multiple steps to test connectivity and correctness of circuitry. These methods are inefficient in some applications. The present invention improves efficiency of the testing process of some electronic systems. One embodiment of the present invention injects a known current into a circuit at a test point by providing a known voltage across a known resistance. The voltage at the test point is measured and the circuit is characterized by a plot of the known voltage minus the measured voltage with respect to the measured voltage. One embodiment is used to improve efficiency in testing advanced functional testers. Since a circuit is characterized by the embodiment contacting one test point, continuity and integrity from each connector pin are tested simultaneously. Thus, the need for a shorting board test is eliminated. Other embodiments are used to test other electrical systems.
A method for circuit characterization comprising:
A circuit characterization tool comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
1. Field of the Invention
The present invention relates to circuit board testing equipment and more specifically to a method and apparatus for testing integrity of electronic circuits.
2. Background Art
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims and accompanying drawings where:
FIG. 1 is a block diagram of an advanced functional tester.
FIG. 2 is a flow diagram of a prior art method for testing advanced functional testers.
The invention is a method and apparatus for characterization of electronic circuitry. En the following description, numerous specific details are set forth to provide a more thorough description of embodiments of the invention. It is apparent, however, to one skilled in the art, that the invention may be practiced without these specific details. In other instances, well known features have not been described in detail so as not to obscure the invention.
Characterization Tool
FIG. 6 illustrates one embodiment of the present invention. The characterization tool (600) has a test voltage input (605). The test voltage input, resistor 1 (610) and resistor 2 (615) are coupled together. Resistor 1, test probe 1 (620), resistor 3 (625) and output 1 (630) are coupled together. Resistor 2, resistor 4 (635) and the positive input of the voltage subtracter (640) are coupled together. Resistor 3, the negative input of the voltage subtractor and resistor 5 (645) are coupled together. Test probe 2 (650) couples to the common voltage (ground) (655). Resistor 4 couples to the common voltage (ground) (660). Resistor 5, the output of the voltage subtractor and output 2 (665) are coupled together.
Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing: marginal…
Computing and data processing
Term ended 4 Feb 2021 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.