120 degree bump placement layout for an integrated circuit power grid
AssigneeSun Microsystems, Inc.
InventorsSudhakar Bobba, Tyler Thorp, Dean Liu
Life of this patent
Estimating the term…
Abstract
A 120 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 120 degree bump placement structures is provided.
Claims18
An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising:
- a first bump disposed on the first metal bar;
- a second bump disposed on the first metal bar;
- and
- a reference bump disposed on the second metal bar,
- wherein the first bump and the second bump, are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees, and
- wherein the value of the angle is dependent on at least one selected from the group consisting of:
- a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
An integrated circuit having a top metal layer, the top metal layer having a first metal bar and a second metal bar, the integrated circuit comprising:
- a first bump disposed on the first metal bar;
- a second bump disposed on the first metal bar;
- and
- a reference bump disposed on the second metal bar,
- wherein the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees, and
- wherein the value of the angle is dependent on at least one selected from the group consisting of:
- a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
A patterned bump array for a power grid of an integrated circuit, comprising:
- a reference bump disposed on a first metal bar;
- a first bump disposed on a second metal bar;
- and
- a second bump disposed on a second metal bar,
- wherein the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees, and
- wherein the value of the angle is dependent on at least one selected from the group consisting of:
- a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
A bump layout for a power grid of an integrated circuit, comprising:
- a reference bump disposed on a first metal bar;
- a first bump disposed on a second metal bar;
- and
- a second bump disposed on a second metal bar,
- wherein the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 120 degrees, and
- wherein the value of the angle is dependent on at least one selected from the group consisting of:
- a desired capacitance, a desired resistance, a desired inductance, a desired bump current flow, a desired bump population on the top metal layer, and desired signal track availability.
Dependencies are inferred from the claim text.