Semiconductor package for multiple high power transistors
AssigneeAdvanced Energy Industries, Inc.
InventorGideon van Zyl
Life of this patent
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Abstract
There is provided by this invention a novel and unique configuration for combining multiple die such as metal oxide field effect transistors (MOSFETS) in high power high frequency applications to prevent internal oscillation. A first embodiment of this invention comprises a split gate design wherein the gate distribution network for multiple semiconductor devices is split to provide individual gate feeds to each device. A second embodiment provides a plurality of semiconductors devices arranged in a configuration such that the reference terminals are connected together at a common point at the approximate center of the configuration that allows external connections to the semiconductor devices' input and output terminals positioned on the outer periphery of the configuration design.
Claims12
A configuration for combining multiple semiconductor devices, comprising:
- a) a supporting structure;
- b) a plurality of semiconductor devices mounted on the supporting structure and disposed to be connected in a parallel configuration;
- c) the plurality of semiconductor devices has a common input terminal, a common output terminal, and a common reference terminal;
- d) each of the semiconductor devices having an input terminal, an output terminal, and a reference terminal;
- e) each semiconductor device input terminal has an electrical connection with an inductance L1 to an input distribution network;
- f) the input distribution network connects each semiconductor device input terminal to a common point where all the semiconductor device input terminals are connected together wherein the inductance between each semiconductor input terminal and the common point of connection is L2;
- and
- g) an inductance L3 between the point where all input terminals of each semiconductor device is connected together and the common input terminal, wherein L2 is at least 10 percent larger than the sum of L1 and L3.
A configuration for combining multiple semiconductor devices, comprising:
- a) a supporting structure;
- b) a plurality of semiconductor devices mounted on the supporting structure;
- c) each of the plurality of semiconductor devices having an input terminal, an output terminal, and a reference terminal;
- d) the plurality of semiconductors devices are arranged in a configuration such that the reference terminals are connected together at a common point at the approximate center of the configuration;
- and
- e) at least two separate external terminals are connected to the common point of connection of the reference terminals.
Dependencies are inferred from the claim text.