Multilayer semiconductor wiring structure with reduced alignment mark area
AssigneeNEC Electronics Corporation
InventorHirofumi Saito
Life of this patent
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Abstract
When the through holes are formed in the first to the eighth insulation layers, an alignment is performed by using an alignment mark provided in the lowermost wiring layer. The alignment marks provided in the insulation layers are formed by being alternately overlapped in two areas of a scribe line having a saucer, thereby, the area occupied by the alignment marks is reduced.
Claims6
A semiconductor device having a multilayer wiring structure in which wiring layers and insulation layers are alternately stacked, and an alignment of each layer is performed by using an alignment mark provided in a predetermined alignment area, comprising:
- alignment marks having through holes provided in said insulation layers, to be used in the alignment of said wiring layers with respect to said insulation layers;
- and
- an alignment mark provided in the lowermost wiring layer, to be used in the alignment of all of said insulation layers.
Dependencies are inferred from the claim text.