US 6,617,655 B1Granted

MOSFET device with multiple gate contacts offset from gate contact area and over source area

AssigneeFairchild Semiconductor Corporation

InventorsMaria Cristina B. Estacio, Margie Tumulak

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Abstract

Careful repositioning of MOSFET gate contacts and increasing of their number makes MOSFET gate contacts more durable and reliable without requiring changes in either the leadframe design or the assembly process. Extension of the under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads not overlying the gate pad metallization minimizes the risk of delamination of the metallization due to thermal and mechanical stresses in assembly and operation. Use of more than one gate pad further reduces such failure risks. Positioning the gate pads sufficiently close to the original gate contact permits use of the same leadframe design and assembly process as would be used for a single gate pad placed directly over the gate contact. The result is a reliable, durable MOSFET gate contact compatible with current assembly methods.

Claims40

Dependent claims

A semiconductor device having a robust and reliable MOSFET gate external connection, comprising:

a semiconductor body having a first surface and a second surface;
a source contact area on the first surface of the semiconductor body;
a drain contact area on the second surface of the semiconductor body;
a gate contact area on the first surface of the semiconductor body and separate from the source contact area;
a source contact metallization layer overlying the source contact area;
a gate contact metallization layer overlying the gate contact area;
a source contact passivation layer overlying the source contact metallization layer and having one or more openings exposing a portion of the surface of the source contact metallization layer;
a gate contact passivation layer overlying the gate contact metallization layer and having one or more openings exposing a portion of the surface of the gate contact metallization layer;
a first insulating layer overlying the gate contact passivation layer and the source contact passivation layer and having one or more openings exposing a portion of the surface of the gate contact metallization layer;
a first conducting metal layer overlying the first insulating layer, connected to the gate contact metallization layer via the one or more openings in the first insulating layer, not overlying exposed areas of the source metallization layer, and partially overlying unexposed areas of the source contact metallization layer;
a second insulating layer overlying the first conducting metal layer and the first insulating layer and having two or more openings each overlying the source contact metallization layer wherein each such opening exposes a portion of the surface of the first conducting metal layer;
a second conducting metal layer having two or more zones each overlying and in contact with one exposed portion of the first conducting metal layer, and each having an outline of size and shape substantially the same as the exposed portion of the outline of the first conducting metal layer;
a metal plating layer having two or more zones each overlying and in contact with one exposed portion of the second conducting metal layer overlying an exposed portion of the first conducting metal layer, and each having an outline of size and shape substantially the same as the exposed portion of the outline of the first conducting metal layer;
and
two or more solder bumps each overlying one metal plating layer zone, and each having an outline of size and shape substantially the same as the exposed portion of the outline of the metal plating layer.

12 more elements

A semiconductor device having a robust and reliable MOSFET gate external connection, comprising:

a semiconductor body having a first surface and a second surface;
a source contact area on the first surface of the semiconductor body;
a drain contact area on the second surface of the semiconductor body;
a gate contact area on the first surface of the semiconductor body and separate from the source contact area;
a source contact conducting extension means overlying the source contact area;
a gate contact conducting extension means overlying the gate contact area;
a source contact protection means overlying the source contact conducting extension means and having one or more openings exposing a portion of the surface of the source contact conducting extension means;
a gate contact protection means overlying the gate contact conducting extension means and having one or more openings exposing a portion of the surface of the gate contact conducting extension means;
a first insulating layer overlying the gate contact protection means and the source contact protection means and having one or more openings exposing a portion of the surface of the gate contact conducting extension means;
a first conducting means overlying the first insulating layer, connected to the gate contact conducting extension means via the one or more openings in the first insulating layer, not overlying exposed areas of the source conducting extension means, and partially overlying unexposed areas of the source contact conducting extension means;
a second insulating layer overlying the first conducting means and the first insulating layer and having two or more openings each overlying the source contact conducting extension means wherein each such opening exposes a portion of the surface of the first conducting means;
a second conducting means having two or more zones each overlying and in contact with one exposed portion of the first conducting means, and each having an outline of size and shape substantially the same as the exposed portion of the outline of the first conducting means;
and
a conducting external connection means having two or more zones each overlying and in contact with one exposed portion of the second conducting means overlying an exposed portion of the first conducting means, and each having an outline of size and shape substantially the same as the exposed portion of the outline of the first conducting means.

11 more elements

A semiconductor device having a robust and reliable MOSFET gate external connection, comprising:

a semiconductor body having a first surface and a second surface;
a source contact area on the first surface of the semiconductor body;
a drain contact area on the second surface of the semiconductor body;
a gate contact area on the first surface of the semiconductor body and separate from the source contact area;
a source contact metallization layer overlying the source contact area;
a gate contact metallization layer overlying the gate contact area;
a source contact passivation layer overlying the source contact metallization layer and having one or more openings exposing a portion of the surface of the source contact metallization layer;
a gate contact passivation layer overlying the gate contact metallization layer and having one or more openings exposing a portion of the surface of the gate contact metallization layer;
a first insulating layer overlying the gate contact passivation layer and the source contact passivation layer and having one or more openings exposing a portion of the surface of the gate contact metallization layer;
a first conducting metal layer overlying the first insulating layer, connected to the gate contact metallization layer via the one or more openings in the first insulating layer;
a second insulating layer overlying the first conducting metal layer and the first insulating layer and having two or more openings each overlying the source contact metallization layer wherein each such opening exposes a portion of the surface of the first conducting metal layer;
and
two or more solder bumps each over the second insulating layer and coupled to the first conducting metal layer.

10 more elements

A semiconductor device having a robust and reliable MOSFET gate external connection, comprising:

a semiconductor body having a first surface and a second surface;
a source contact area on the first surface of the semiconductor body;
a drain contact area on the second surface of the semiconductor body;
a gate contact area on the first surface of the semiconductor body and separate from the source contact area;
a source contact metallization layer overlying the source contact area;
a gate contact metallization layer overlying the gate contact area;
a source contact passivation layer overlying the source contact metallization layer and having one or more openings exposing a portion of the surface of the source contact metallization layer;
a gate contact passivation layer overlying the gate contact metallization layer and having one or more openings exposing a portion of the surface of the gate contact metallization layer;
a first insulating layer overlying the gate contact passivation layer and the source contact passivation layer and having one or more openings exposing a portion of the surface of the gate contact metallization layer;
a first conducting metal layer overlying the first insulating layer, connected to the gate contact metallization layer via the one or more openings in the first insulating layer;
a second insulating layer overlying the first conducting metal layer and the first insulating layer and having two or more openings each overlying the source contact metallization layer wherein each such opening exposes a portion of the surface of the first conducting metal layer;
a second conducting metal layer having two or more zones each overlying and in contact with one of the exposed portions of the first conducting metal layer;
a metal plating layer having two or more zones each overlying and in contact with one exposed portion of the second conducting metal layer overlying an exposed portion of the first conducting metal layer;
and
a conducting external connection means having two or more zones each overlying and coupled to the first conducting layer.

12 more elements

Dependencies are inferred from the claim text.