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US 6,617,646 B2Granted
Reduced substrate capacitance high performance SOI process
AssigneeElantec Semiconductor, Inc.
InventorSameer Parab
Life of this patent
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Abstract
A silicon on insulator substrate is provided to include the following: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from the layer of bonding material upward into the device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer. The silicon on insulator substrate with this configuration can be made with a minimal possible thickness.
Claims12
A silicon on insulator substrate, comprising:
- a layer of bonding material;
- a device wafer, the device wafer including at least one buried impurity region extending from said layer of bonding material upward into said device wafer;
- and
- an epitaxial silicon layer provided on a second surface of the device wafer.
1 more element
A semiconductor device comprising:
- a handle wafer;
- a layer of bonding material;
- a device wafer, the device wafer including at least one buried impurity region extending from said layer of bonding material upward into said device wafer;
- an epitaxial silicon layer provided on a second surface of the device wafer;
- at least one active region provided in the device wafer and epitaxial silicon layer;
- and
- a buried region provided in the device wafer having a greater concentration of dopant atoms at a point in the device wafer closer to the bonding material than at a second point farther from the bonding material.
4 more elements
Dependencies are inferred from the claim text.