US 6,617,637 B1Granted

Electrically erasable programmable logic device

AssigneeeMemory Technology Inc.

InventorsChing-Hsiang Hsu, Yen-Tai Lin, Chih-Hsun Chu, Shih-Jye Shen, Ching-Sung Yang, Ming-Chou Ho

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Abstract

An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.

Claims33

Dependent claims

An electrically erasable programmable logic device (EEPLD) formed in a semiconductor substrate, the EEPLD having an individual word line, a bit line, a source line, an erase line and a well contact, the EEPLD comprising:

a second conductivity type well disposed in the semiconductor substrate, the well being electrically connected to the well contact;
a first source region of a first conductivity type formed in the well region, the first source region being electrically connected to the source line;
an erase region of the second conductivity type formed in the first source region, the erase region being electrically connected to the erase line;
a first drain region of the first conductivity type formed in the well region;
a first channel region defined between the first drain region and the erase region;
a floating gate formed over the first channel region;
a second source region of the first conductivity type formed in the well region;
a second drain region of the first conductivity type formed in the well region, the second drain region being electrically connected to the bit line;
a second channel region defined between the second source region and the second drain region;
and
a gate formed over the second channel region, the gate being electrically connected to the word line.

8 more elements

A memory array comprising:

a plurality of electrically erasable programmable logic devices arranged in rows and columns, each of the electrically erasable programmable logic devices being formed in a semiconductor substrate, and comprising:
a second conductivity type well disposed in the semiconductor substrate, the well being electrically connected to a well contact;
a first source region of the first conductivity type formed in the well region, the first source region being electrically connected to a source line;
an erase region of the second conductivity type formed in the first source region, the erase region being electrically connected to an erase line;
a first drain region of the first conductivity type formed in the well region;
a first channel region defined between the first drain region and erase region;
a floating gate formed over the first channel region;
a second source region of the first conductivity type formed in the well region;
a second drain region of the first conductivity type formed in the well region,
the second drain region being electrically connected to a bit line;
a second channel region defined between the second source region and the second drain region;
and
a gate formed over the second channel region, the gate being electrically connected to a word line;
a plurality of the word lines, each of the word lines being connected to each gate in a row of the electrically erasable programmable logic devices;
a plurality of the bit lines, each of the bit lines being electrically connected to each second drain region in a column of the electrically erasable programmable logic devices:
a plurality of the source lines, each of the source lines being electrically connected to each first source region in a row of the electrically erasable programmable logic devices;
and
a plurality of the erase lines, each of the erase lines being electrically connected to each erase region.

15 more elements

Dependencies are inferred from the claim text.