Nonvolatile memory structures and fabrication methods

#The present invention relates to semiconductor technology, and more particularly to nonvolatile memories.

#FIGS. 1-8 illustrate fabrication of a conventional nonvolatile stacked-gate flash memory described in U.S. Pat. No. 6,013,551 issued Jan. 11, 2000 to J. Chen et al. Silicon oxide layer 108 (“tunnel oxide”) is grown on P-doped silicon substrate 150. Doped polysilicon 124 is deposited over oxide 108. Polysilicon 124 will provide floating gates for memory cell transistors.

#Mask 106 is formed over the structure. Polysilicon 124, oxide 108, and substrate 150 are etched through the mask openings. Trenches 910 are formed in the substrate as a result (FIG. 2).

#FIGS. 1-7 are cross section illustrations of a prior art flash memory at different stages of fabrication.

#FIG. 8 is a top view of the memory of FIGS. 1-7.

#FIG. 9A is a top view of a memory according to some embodiments of the present invention.

#In the drawings, the reference numbers are used as indicated in the following table. The list of the reference numbers in this table is not exhaustive. The description of the features is not complete, and is not limiting. For example, silicon dioxide can be replaced with other insulators. Not all of the functions described for a reference number have to be present in the invention, and also functions not described can be present.

#Reference Number Feature 98 Insulator isolating the floating gates 124 from the control gates 128 108 Tunneling oxide 124 Floating gates 128 Control gates 130 Bitlines 134 Bitline regions of memory cells 138 Bitline contacts to memory cells 144 Source lines 150 Isolated substrate region 520 Wordlines 710 Stacks including the floating and control gates 720 Silicon nitride at the top of stacks 710 901 Memory array 903 Silicon nitride on sidewalls of stacks 710 904 Photoresist mask used to pattern the floating gate polysilicon 124 and the isolation trenches 905 Substrate 910 Isolation trench 1010 Insulation in isolation trenches 1014 Photoresist used to pattern the stacks 710 1103 N-region isolating the substrate region 150 from below 1105 N-region isolating the substrate region 150 laterally on all sides 1203 Silicon nitride that serves as a stop layer during the etch of trench insulation 1010 1510 Silicon dioxide insulating the floating gate sidewalls 1603 Peripheral areas 1710 Photoresist mask used to etch the polysilicon 520 1810 Gate oxide for select transistors 2110 Deep source line implant 2401 Source line and bitline region implant 2501 Photoresist mask used to form wordline extensions and peripheral transistor gates 2605 Silicide on top of peripheral transistor gates 2701 Gap in which wordline extensions 520E are formed 2703.1, Memory array sections 2703.2 2710 Oxide deposited before patterning isolation trenches 2810 Photoresist used to pattern isolation trenches 3301 Silicide over source lines 144 4201 Voltage generator

#The description of the preferred embodiments is illustrative and not limiting. The invention is not limited by any particular dimensions, materials, processing steps, doping levels, crystal orientation, layer thicknesses, layouts, or any other features, unless expressly stated otherwise.