Vertical read-only memory and fabrication thereof

#1. Field of Invention

#The present invention relates to a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a vertical read-only memory (ROM) and the fabrication thereof.

#2. Description of Related Art

#The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

#FIG. 1 schematically illustrates a vertical read-only memory provided in the first embodiment of this invention; and

#FIG. 2A˜2Q schematically illustrate a process flow of fabricating a vertical read-only memory in a cross-sectional view in the second embodiment of this invention.

#FIG. 1 schematically illustrates a vertical read-only memory provided in the first embodiment of this invention.

#Refer to FIG. 1, the vertical read-only memory comprises a gate conductive layer 104 on a substrate 100 having a protruding region 102 and two depressed regions 108, two conductive layers 114 serving as two bit-lines, a word-line 116, a source/drain 106a/106b, and two coding regions 110. The gate conductive layer 104 is located on the protruding region 102, while the conductive layer 114 is located on the depressed regions 108 and electrically connects with the source/drain 106a/106b. The source/drain 106a/106b is located in the depressed regions 108 and the two coding regions 110 are each located in the substrate 100 of one side-wall of the protruding region 102. The word-line 116 is disposed on the substrate 100 and electrically connects with the gate conductive layer 104. Moreover, a gate oxide layer 112 is disposed between the gate conductive layer 104 and the substrate 100. An insulating layer 118 is disposed between the conductive layer 114 and the side-walls of the depressed regions 108 and a silicon oxide layer 120 is disposed between the conductive layer 114 and the word-line 116.

#Moreover, the coding regions 110 are formed by a coding implantation using an ion with a second conductivity type, which is different from a first conductivity type of the dopants that are originally in the coding regions 110. The concentration of the dopants of the second conductivity type is smaller than the concentration of the dopants of the first conductivity type, so that the coding region 110 implanted during the coding implantation is of a low concentrated first conductivity type and thereby has a lower threshold voltage.