Pad layout and lead layout in semiconductor device having a center circuit

#The present invention generally relates to a semiconductor device and, more particularly, to a layout for pads and leads for a semiconductor device.

#Generally, in a semiconductor device, pads for leading out electrodes from an internal circuit are arranged in a row along the periphery of the chip or in the central portion thereof. FIGS. 1 to 3 show various examples of conventional pad layouts and lead layouts in which respective pads of the semiconductor chip are connected with the leads by wire bonding (in a state prior to the packaging). FIG. 1 shows the layout which is most widely used and in which pads 12 are arranged along the four sides of the semiconductor chip 11. The chip 11 is mounted on a bed B and the end portions of the leads 13 and the pads 12 are respectively connected via bonding wires 14. FIG. 2 shows the LOC (Lead On Chip) structure in which pads 12 are arranged along two opposite sides of a chip 11 and the end portions of leads 13 which are provided on the chip 11 are connected to the respective pads 12 via bonding wires 14. FIG. 3 shows the LOC structure of center pad type in which pads 12 are arranged in a row in the central portion of a chip 11 and the end portions of leads 13 which are provided on the chip 11 are connected to the respective pads 12 via bonding wires 14.

#The various types of pad layouts and lead layouts shown in FIGS. 1 to 3 are described in Mitake et al., “Multi-byte 16 Mbit DRAM”, NEC Technical Report, Vol. 46, No. 2/1993, pages 94-97; U.S. Pat. No. 5,072,280 to Matsukura entitled “Resin Sealed Semiconductor Device”; and the article “Starting of Full-Scale Study of LOC for Second Generation 16 Mbit DRAM”, November 1991 issue of NIKKEI MICRODEVICES by NIKKEI BP Co., pages 79-83. Each of these documents is incorporated herein by reference.

#The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

#FIG. 1 is a plan view for illustrating a conventional semiconductor device in which pads and leads of the semiconductor chip are connected by wire bonding;

#FIG. 2 is a plan view for illustrating another conventional semiconductor device in which pads and leads of the semiconductor chip are connected by wire bonding;

#FIG. 9 is a block diagram showing the schematic construction of a 16 Mbit semiconductor memory device, for illustrating a semiconductor device according to a first embodiment of this invention. The semiconductor memory device includes 4-Mbit memory cell arrays 21-1 to 21-4. Each of the memory cell arrays 21-1 to 21-4 is constructed by eight sub-arrays of 512 kbits and sense amplifiers 22-1, 22-2, 22-3, 22-4 are arranged between the sub-arrays. Each of the sense amplifiers 22-1, 22-2, 22-3, 22-4 is commonly used by the adjacent sub-arrays. In each of the sub-arrays, word lines WL, bit lines BL, and memory cells MC connected to the word lines WL and bit lines BL are formed. Common column selection lines CSL are formed to extend over the sub-arrays in the respective memory cell arrays 21-1 to 21-4 and each of them is commonly used by the sub-arrays in a corresponding one of the arrays.

#In an area between the memory cell arrays 21-1 and 21-3, two rows of pad groups 12-1a and 12-2a are disposed. Likewise, in an area between the memory cell arrays 21-2 and 21-4, two rows of pad groups 12-1b and 12-2b are disposed. The pads of the pad group 12-1a are shifted or offset from the corresponding pads of the pad group 12-2a by ½ pitch, and the pads of the pad group 12-1b are shifted from the corresponding pads of the pad group 12-2b by ½ pitch. Pitch refers to the distance between the centers of adjacent pads. In an area between the memory cell array 21-1 and the pad groups 12-1a, 12-2a, a peripheral circuit 23-1 is disposed. The peripheral circuit 23-1 contains bus lines and output buffers. In an area between the memory cell array 21-2 and the pad groups 12-1b, 12-2b, a peripheral circuit 23-2 is disposed. The peripheral circuit 23-2 contains bus lines. Further, in an area between the memory cell array 21-3 and the pad groups 12-1a, 12-2a, a peripheral circuit 23-3 is disposed. The peripheral circuit 23-3 contains bus lines and output buffers. In an area between the memory cell array 21-4 and the pad groups 12-1b, 12-2b, a peripheral circuit 23-4 is disposed. The peripheral circuit 23-4 contains bus lines.

#In an area between the peripheral circuit 23-1 and the memory cell array 21-1, a row decoder 24-1 for selecting the word lines WL of memory cell array 21-1 is disposed, and in an area between the peripheral circuit 23-2 and the memory cell array 21-2, a row decoder 24-2 for selecting the word lines of memory cell array 21-2 is disposed. In an area between the peripheral circuit 23-3 and the memory cell array 21-3, a row decoder 24-3 for selecting the word lines of memory cell array 21-3 is disposed, and in an area between the peripheral circuit 23-4 and the memory cell array 21-4, a row decoder 24-4 for selecting the word lines of memory cell array 21-4 is disposed.