Semiconductor device and a semiconductor integrated circuit
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsHongyong Zhang, Naoaki Yamaguchi, Yasuhiko Takemura
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Abstract
The present invention relates to a semiconductor device and a semiconductor integrated circuit. The semiconductor device comprises a semiconductor layer comprising a channel region, a source and a drain regions and at least one lower impurity concentration region interposed between the channel region and the source or the drain region. The source and the drain regions comprise metal silicide region. The lower impurity concentration region is not covered with the metal silicide region. The operational speed of the circuit can be improved, and the leak current of the transistor can be reduced.
Claims29
A semiconductor device comprising:
- a semiconductor region comprising a channel region, a source region, a drain region, and at least one lower impurity concentration region interposed between said channel region and said source or said drain region;
- a gate insulating film on at least said channel region;
- and
- a gate electrode on said gate insulating film,
- wherein said source and said drain regions comprise metal silicide regions, and
- wherein said lower impurity concentration region is not covered with said metal silicide region.
A semiconductor integrated circuit comprising:
- a semiconductor region comprising a channel region, a source region, a drain region, and at least one lower impurity concentration region interposed between said channel region and said source or said drain region;
- a gate insulating film on at least said channel region;
- and
- a gate electrode on said gate insulating film,
- wherein said source and said drain regions comprise metal silicide regions, and
- wherein said lower impurity concentration region is not covered with said metal silicide region.
A semiconductor device comprising:
- a semiconductor layer on an insulating surface, said semiconductor layer comprising a channel region, a source region, a drain region, and at least one lower impurity concentration region interposed between said channel region and said source or said drain region;
- a gate insulating film on at least said channel region;
- and
- a gate electrode on said gate insulating film,
- wherein said source and said drain regions comprise metal slicide regions, and
- wherein said lower impurity concentration region is not covered with said metal silicide region.
A semiconductor integrated circuit comprising:
- a semiconductor layer on an insulating surface, said semiconductor layer comprising a channel region, a source region, a drain region and at least one lower impurity concentration region interposed between said channel region and said source or said drain region;
- a gate insulating film on at least said channel region;
- and
- a gate electrode adjacent to said gate insulating film,
- wherein said source and said drain regions comprise metal silicide regions, and
- wherein said lower impurity concentration region is not covered with said metal silicide region.
A semiconductor device comprising:
- a semiconductor region comprising a channel region, a pair of lower impurity concentration regions between which said channel region extends, and source and drain regions adjacent to said lower impurity concentration regions;
- a gate insulating film on at least said channel region;
- and
- a gate electrode on said gate insulating film,
- wherein said source and drain regions comprise metal silicide regions, and
- wherein said lower impurity concentration regions are not covered with said metal silicide regions.
A semiconductor device comprising:
- a semiconductor layer on an insulating surface, said semiconductor layer comprising a channel region, a pair of lower impurity concentration regions between which said channel region extends, and source and drain regions adjacent to said lower impurity concentration regions;
- a gate insulating film on at least said channel region;
- and
- a gate electrode on said gate insulating film,
- wherein said source and drain regions comprise metal silicide regions, and
- wherein said lower impurity concentration regions are not covered with said metal silicide regions.
A semiconductor device comprising:
- a semiconductor region comprising a channel region, a source region, a drain region, and at least one lower impurity concentration region interposed between said channel region and said source or drain region;
- a gate insulating film on at least said channel region;
- and
- a gate electrode on said gate insulating film,
- wherein said source and drain regions comprise metal silicide regions, and
- wherein said lower impurity concentration region is not covered with said metal silicide region, and
- wherein said lower impurity concentration region is in contact with one of the metal silicide regions.
Dependencies are inferred from the claim text.